<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> This will cause amdgpu startup to fail if the firmware does not exist: this should either wait until the firmware is available or not return an error value if -ENOENT is returned from request_firmware </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">From: David Francis <David.Francis@amd.com> Sent: September 7, 2018 10:16:56 AM To: amd-gfx@lists.freedesktop.org Cc: Francis, David Subject: [PATCH] drm/amd: Add DMCU firmware loading on raven <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">[Why] DMCU (Display MicroController Unit) is an on-GPU microcontroller in AMD graphics cards that is used in features for embedded displays such as Panel Self-Refresh DMCU is part of the DM IP block [How] DMCU is added as an option in the enum AMDGPU_UCODE_ID DMCU needs two pieces of firmware - the initial eram and the interrupt vectors. These are treated as seperate pieces of firmware and loaded by PSP The loading occurs in the sw_init hook of DM Signed-off-by: David Francis <David.Francis@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2 + drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 93 +++++++++++++++++++ 3 files changed, 101 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index b358e7519987..38d3af317aa2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -196,6 +196,8 @@ enum AMDGPU_UCODE_ID { AMDGPU_UCODE_ID_UVD1, AMDGPU_UCODE_ID_VCE, AMDGPU_UCODE_ID_VCN, + AMDGPU_UCODE_ID_DMCU_ERAM, + AMDGPU_UCODE_ID_DMCU_INTV, AMDGPU_UCODE_ID_MAXIMUM, }; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 02be34e72ed9..240dc8c85867 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -91,6 +91,12 @@ psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type * case AMDGPU_UCODE_ID_VCN: *type = GFX_FW_TYPE_VCN; break; + case AMDGPU_UCODE_ID_DMCU_ERAM: + *type = GFX_FW_TYPE_DMCU_ERAM; + break; + case AMDGPU_UCODE_ID_DMCU_INTV: + *type = GFX_FW_TYPE_DMCU_ISR; + break; case AMDGPU_UCODE_ID_MAXIMUM: default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5103eba75cb3..4619f624f346 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -30,6 +30,7 @@ #include "vid.h" #include "amdgpu.h" #include "amdgpu_display.h" +#include "amdgpu_ucode.h" #include "atom.h" #include "amdgpu_dm.h" #include "amdgpu_pm.h" @@ -50,6 +51,7 @@ #include <linux/version.h> #include <linux/types.h> #include <linux/pm_runtime.h> +#include <linux/firmware.h> #include <drm/drmP.h> #include <drm/drm_atomic.h> @@ -71,6 +73,12 @@ #include "modules/inc/mod_freesync.h" +#define FIRMWARE_RAVEN_DMCU_ERAM "amdgpu/raven_dmcu_eram.bin" +MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU_ERAM); + +#define FIRMWARE_RAVEN_DMCU_INTV "amdgpu/raven_dmcu_intv.bin" +MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU_INTV); + /* basic init/fini API */ static int amdgpu_dm_init(struct amdgpu_device *adev); static void amdgpu_dm_fini(struct amdgpu_device *adev); @@ -516,6 +524,91 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) static int dm_sw_init(void *handle) { + const struct firmware *fw; + const char *fw_name_dmcu_eram; + const char *fw_name_dmcu_intv; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; + + switch(adev->asic_type) { + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_MULLINS: + case CHIP_TONGA: + case CHIP_FIJI: + case CHIP_CARRIZO: + case CHIP_STONEY: + case CHIP_POLARIS11: + case CHIP_POLARIS10: + case CHIP_POLARIS12: + case CHIP_VEGAM: + case CHIP_VEGA10: + case CHIP_VEGA12: + case CHIP_VEGA20: + return 0; + case CHIP_RAVEN: + fw_name_dmcu_eram = FIRMWARE_RAVEN_DMCU_ERAM; + fw_name_dmcu_intv = FIRMWARE_RAVEN_DMCU_INTV; + break; + default: + DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); + return -1; + } + + r = request_firmware(&fw, fw_name_dmcu_eram, adev->dev); + if (r) { + dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", + fw_name_dmcu_eram); + return r; + } + + r = amdgpu_ucode_validate(fw); + if (r) { + dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", + fw_name_dmcu_eram); + release_firmware(fw); + fw = NULL; + return r; + } + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + const struct common_firmware_header *hdr; + hdr = (const struct common_firmware_header *)fw->data; + adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; + adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); + DRM_INFO("PSP loading DMCU_ERAM firmware\n"); + } + + r = request_firmware(&fw, fw_name_dmcu_intv, adev->dev); + if (r) { + dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", + fw_name_dmcu_intv); + return r; + } + + r = amdgpu_ucode_validate(fw); + if (r) { + dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", + fw_name_dmcu_intv); + release_firmware(fw); + fw = NULL; + return r; + } + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + const struct common_firmware_header *hdr; + hdr = (const struct common_firmware_header *)fw->data; + adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; + adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); + DRM_INFO("PSP loading DMCU_INTV firmware\n"); + } + return 0; } -- 2.17.1 </div> </div> </body> </html>