<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> <p style="margin-top:0;margin-bottom:0"><span>It's trivial to add the metadata/version headers to the existing firmware, so that is not an issue.</span> The issue is with the firmware itself. If we used the existing firmware, we'd have to add a bunch of really ugly hacks in the driver to work around the current limitations. </p> <p style="margin-top:0;margin-bottom:0"><br> </p> <p style="margin-top:0;margin-bottom:0">Alex</p> <p style="margin-top:0;margin-bottom:0"><br> </p> </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Mike Lothian <mike@fireburn.co.uk><br> <b>Sent:</b> Monday, October 8, 2018 8:16:01 AM<br> <b>To:</b> Koenig, Christian<br> <b>Cc:</b> Mauro Rossi; Wentland, Harry; amd-gfx@lists.freedesktop.org<br> <b>Subject:</b> Re: [RFC] drm/amd/display: add SI support to AMD DC</font> <div> </div> </div> <meta content="text/html; charset=utf-8"> <div> <div dir="ltr">I thought it just required the existing firmware, with padding / extra info put around it?<br> <br> <div class="x_gmail_quote"> <div dir="ltr">On Mon, 8 Oct 2018 at 12:29 Christian König <<a href="mailto:ckoenig.leichtzumerken@gmail.com">ckoenig.leichtzumerken@gmail.com</a>> wrote:<br> </div> <blockquote class="x_gmail_quote" style="margin:0 0 0 .8ex; border-left:1px #ccc solid; padding-left:1ex"> <div bgcolor="#FFFFFF"> <div class="x_m_-1296221763677580797moz-cite-prefix">UVD/VCE on SI with amdgpu would need new firmware.<br> <br> And so far we never had time to actually look into releasing that firmware.<br> <br> Regards,<br> Christian.</div> </div> <div bgcolor="#FFFFFF"> <div class="x_m_-1296221763677580797moz-cite-prefix"><br> <br> Am 08.10.2018 um 13:22 schrieb Mauro Rossi:<br> </div> </div> <div bgcolor="#FFFFFF"> <blockquote type="cite"> <div dir="ltr">Hi Mike,<br> <div class="x_gmail_quote"> <div dir="ltr">On Mon, Oct 8, 2018 at 1:00 PM Mike Lothian <<a href="mailto:mike@fireburn.co.uk" target="_blank">mike@fireburn.co.uk</a>> wrote:<br> </div> <blockquote class="x_gmail_quote" style="margin:0 0 0 .8ex; border-left:1px #ccc solid; padding-left:1ex"> <div dir="ltr">Hi Mauro <div><br> </div> <div>Do you know if there are any plans to add in UVD support on SI too?</div> <div><br> </div> <div>Thanks</div> <div><br> </div> <div>Mike</div> </div> </blockquote> <div><br> </div> <div>At the moment my focus is on getting a conformant, working and stable</div> <div>implementation of Atomic Display Framework, with the objective to have it</div> <div>upstreamed to amd-gfx branch, then staging (drm-next) and maybe merged in linux kernel.</div> <div><br> </div> <div>To be honest my attempt is based on code paths inspection and mimicking,</div> <div>so in this moment I do not even know the state of UVD and what changes are needed,</div> <div>but, based on what I saw for DCE6 support addition on top of DCE8,</div> <div>covering all compatible HW modules makes a lot of sense and it is an opportunity to exploit,</div> <div>if feasible.</div> <div><br> </div> <div>For this to happen in most complete and reliable way the feedback of staff who worked on DAL/DC</div> <div>will be essential, because what I did now was to adapt code for DCE8 to work for DCE6,</div> <div>but it was like an "optimistic monkey with a keyboard" approach, with all due respect for monkeys with keyboards,</div> <div>:-) I may have missed dozen of changes.</div> <div><br> </div> <div>Mauro</div> <div> </div> <blockquote class="x_gmail_quote" style="margin:0 0 0 .8ex; border-left:1px #ccc solid; padding-left:1ex"> <br> <div class="x_gmail_quote"> <div dir="ltr">On Mon, 8 Oct 2018 at 03:24 Mauro Rossi <<a href="mailto:issor.oruam@gmail.com" target="_blank">issor.oruam@gmail.com</a>> wrote:<br> </div> <blockquote class="x_gmail_quote" style="margin:0 0 0 .8ex; border-left:1px #ccc solid; padding-left:1ex"> [PATCH 01/10] drm/amd/display: add asics info for SI parts<br> [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support<br> [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support<br> [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6<br> [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6<br> [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6<br> [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6<br> [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support<br> [PATCH 09/10] drm/amdgpu: enable DC support for SI parts<br> [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig<br> <br> The series adds preliminar SI support as a Proof Of Concept, <br> based on the idea that DCE6 is similar to DCE8, to be reviewed and refined<br> <br> Android-x86 need/motivation lies in the following chain of dependencies: <br> Vulkan radv requires gbm gralloc prime_fd support,<br> gbm gralloc requires drm hwcomposer,<br> drm hwcomposer requires Atomic Display Framework, <br> Atomic Display Framework requires AMD DC, currently not supporting SI.<br> <br> So the goals are:<br> 1) to get Vulkan radv working on SI parts for android-x86.<br> 2) to remove the gap in SI (GCN 1st gen) not having atomic support. <br> <br> DCE6 specific code was implemented as a replica of existing DCE8 support<br> and based on how DCE8 specific code was added on top of DCE10,11 support<br> by adding dce60* sources, functions, macros for each existing in dce80*<br> <br> CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC<br> <br> During this first iteration of review, there are aspects to verify:<br> - dce60 code has been added mechanically, so there may be redundancies <br> and space for refactoring part of the code<br> - dce60_resources was having too many building errors due to missing DCE6 macros<br> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers<br> were used for the PoC<br> - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers<br> were used for the PoC<br> - gfx6 may require some ad hoc initialization, skipped for the moment<br> - Hainan specific code requires review, as some documentation and code paths<br> seem to point that famility may not have DCE6, please confirm<br> - video decoding blocks code have not been touched<br> - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics<br> - dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics<br> - dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics<br> - dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics<br> - dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics<br> - dc/amdgpu_dm/* changes may be incomplete<br> - Any other omissis to be reviewed<br> - Feedback on best testing strategy required<br> <br> Review from an expert of the DC impacted modules is recommended<br> <br> SW Layer<br> /===============================================================\<br> | DC Display Timing Mode Asic |<br> | Interface Service Service Manager Capability* |<br> | |<br> | Display Topology Display Link Adapter |<br> | Path Manager Capability Service Service |<br> | Service |<br> |---------------------------------------------------------------|<br> | GPIO* IRQ I2cAux HW BIOS |<br> | Service** Manager* Sequencer* Parser* |<br> | |<br> | Connector Encoder Audio GPU Controller |<br> | |<br> \===============================================================/<br> HW Layer<br> <br> Legend: <br> *dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers<br> **dce60 support was added using dce_8_0_{d,sh_mask}.h headers<br> <br> Android-x86 preliminary tests results:<br> <br> [Boots with drm gralloc]<br> 3DMark Slingshot<br> GFXbench OpenGLES benchmarks OK<br> V1 GPU benchmark (OpenGLES) OK<br> Regression in Google Chrome, Youtube (app does not show up)<br> Regression in Olympus Rising, Chicken Invaders (app does not show up)<br> <br> [Boots with drm hwcomposer + gbm gralloc]<br> Google Chrome, Youtube are OK<br> Vulkan radv HAL API becomes available with hwc+gbm gralloc<br> V1 GPU benchmark (Vulkan API) OK<br> Sacha Willems examples OK<br> Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead<br> <br> Kind regards<br> <br> Mauro Rossi<br> android-x86 team<br> <br> _______________________________________________<br> amd-gfx mailing list<br> <a href="mailto:amd-gfx@lists.freedesktop.org" target="_blank">amd-gfx@lists.freedesktop.org</a><br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> </blockquote> </div> </blockquote> </div> </div> <br> <fieldset class="x_m_-1296221763677580797mimeAttachmentHeader"></fieldset> <br> <pre>_______________________________________________ amd-gfx mailing list <a class="x_m_-1296221763677580797moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org" target="_blank">amd-gfx@lists.freedesktop.org</a> <a class="x_m_-1296221763677580797moz-txt-link-freetext" href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" target="_blank">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a> </pre> </blockquote> <br> </div> </blockquote> </div> </div> </div> </body> </html>