<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> <p style="margin-top:0;margin-bottom:0">Acked-by: Alex Deucher <alexander.deucher@amd.com><br> </p> </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Zhu, James <James.Zhu@amd.com><br> <b>Sent:</b> Tuesday, October 16, 2018 10:15:01 AM<br> <b>To:</b> amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> jzhums@gmail.com; dri-devel@lists.freedesktop.org; kbuild@01.org; kbuild-all@01.org; dan.carpenter@oracle.com<br> <b>Subject:</b> [PATCH] drm/amdgpu/vcn:Fix uninitialized symbol error</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">ret_code should be initialized with 0. The check of read/write<br> ptr should be activate when UVD_POWER_STATUS_TILES is off.<br> <br> Signed-off-by: James Zhu <James.Zhu@amd.com><br> ---<br> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--<br> 1 file changed, 2 insertions(+), 2 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c<br> index bc64706..eae9092 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c<br> @@ -1165,14 +1165,14 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)<br> <br> static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)<br> {<br> - int ret_code;<br> + int ret_code = 0;<br> <br> /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */<br> SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,<br> UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,<br> UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);<br> <br> - if (ret_code) {<br> + if (!ret_code) {<br> int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;<br> /* wait for read ptr to be equal to write ptr */<br> SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);<br> -- <br> 2.7.4<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> </div> </span></font></div> </body> </html>