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<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Wednesday, October 17, 2018 5:21:54 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhu, Rex; Deucher, Alexander; Quan, Evan<br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: error out when force clock level under auto dpm mode V2</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Forcing clock level is supported under manual dpm mode only. Error out<br>
when trying to set under manual mode. Instead of doing nothing and<br>
reporting success.<br>
<br>
V2: update for mclk/pcie clock level settings also<br>
<br>
Change-Id: I2af32be5ebd4323a98cb48da88b22177a68fbdb0<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        | 15 ++++++++++++---<br>
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 11 +++++++----<br>
 2 files changed, 19 insertions(+), 7 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
index 94055a485e01..59cc678de8c1 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
@@ -704,7 +704,10 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,<br>
                 return ret;<br>
 <br>
         if (adev->powerplay.pp_funcs->force_clock_level)<br>
-               amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);<br>
+               ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);<br>
+<br>
+       if (ret)<br>
+               return -EINVAL;<br>
 <br>
         return count;<br>
 }<br>
@@ -737,7 +740,10 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,<br>
                 return ret;<br>
 <br>
         if (adev->powerplay.pp_funcs->force_clock_level)<br>
-               amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);<br>
+               ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);<br>
+<br>
+       if (ret)<br>
+               return -EINVAL;<br>
 <br>
         return count;<br>
 }<br>
@@ -770,7 +776,10 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,<br>
                 return ret;<br>
 <br>
         if (adev->powerplay.pp_funcs->force_clock_level)<br>
-               amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);<br>
+               ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);<br>
+<br>
+       if (ret)<br>
+               return -EINVAL;<br>
 <br>
         return count;<br>
 }<br>
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
index e8964cae6b93..da9ff2cc2777 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
@@ -723,11 +723,14 @@ static int pp_dpm_force_clock_level(void *handle,<br>
                 pr_info("%s was not implemented.\n", __func__);<br>
                 return 0;<br>
         }<br>
+<br>
+       if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {<br>
+               pr_info("force clock level is for dpm manual mode only.\n");<br>
+               return -EINVAL;<br>
+       }<br>
+<br>
         mutex_lock(&hwmgr->smu_lock);<br>
-       if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)<br>
-               ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);<br>
-       else<br>
-               ret = -EINVAL;<br>
+       ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);<br>
         mutex_unlock(&hwmgr->smu_lock);<br>
         return ret;<br>
 }<br>
-- <br>
2.19.1<br>
<br>
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