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<p style="margin-top:0; margin-bottom:0">Please include a patch description on 2 and 3, with that fixed, series is:</p>
<p style="margin-top:0; margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Zhao, Yong<br>
<b>Sent:</b> Thursday, October 18, 2018 5:13:04 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org; brahma_sw_dev<br>
<b>Cc:</b> Zhao, Yong<br>
<b>Subject:</b> [PATCH 3/3] drm/amdkfd: Use functions from amdgpu for setting up page table base</font>
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<div class="PlainText">Change-Id: I42eb2e41ce21b4a6ea0c8394dcc762ee92b2ca5e<br>
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 12 +++---------<br>
1 file changed, 3 insertions(+), 9 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
index 4b79639..223bbc1 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
@@ -46,6 +46,7 @@<br>
#include "v9_structs.h"<br>
#include "soc15.h"<br>
#include "soc15d.h"<br>
+#include "gmc_v9_0.h"<br>
<br>
/* HACK: MMHUB and GC both have VM-related register with the same<br>
* names but different offsets. Define the MMHUB register we need here<br>
@@ -59,11 +60,6 @@<br>
#define mmMMHUB_VM_INVALIDATE_ENG16_ACK 0x0705<br>
#define mmMMHUB_VM_INVALIDATE_ENG16_ACK_BASE_IDX 0<br>
<br>
-#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b<br>
-#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0<br>
-#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c<br>
-#define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0<br>
-<br>
#define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727<br>
#define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0<br>
#define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728<br>
@@ -1018,9 +1014,7 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,<br>
* now, all processes share the same address space size, like<br>
* on GFX8 and older.<br>
*/<br>
- WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));<br>
- WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));<br>
+ mmhub_v1_0_setup_vm_pt_regs(adev, vmid, base);<br>
<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));<br>
+ gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, base);<br>
}<br>
-- <br>
2.7.4<br>
<br>
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