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<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Christian König <ckoenig.leichtzumerken@gmail.com><br>
<b>Sent:</b> Friday, October 26, 2018 6:59:21 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Subject:</b> [PATCH libdrm] amdgpu: add VM test to exercise max/min address space</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Make sure the kernel doesn't crash if we map something at the minimum/maximum address.<br>
<br>
Signed-off-by: Christian König <christian.koenig@amd.com><br>
---<br>
 tests/amdgpu/vm_tests.c | 45 ++++++++++++++++++++++++++++++++++++++++-<br>
 1 file changed, 44 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c<br>
index 7b6dc5d6..bbdeef4d 100644<br>
--- a/tests/amdgpu/vm_tests.c<br>
+++ b/tests/amdgpu/vm_tests.c<br>
@@ -31,8 +31,8 @@ static  amdgpu_device_handle device_handle;<br>
 static  uint32_t  major_version;<br>
 static  uint32_t  minor_version;<br>
 <br>
-<br>
 static void amdgpu_vmid_reserve_test(void);<br>
+static void amdgpu_vm_mapping_test(void);<br>
 <br>
 CU_BOOL suite_vm_tests_enable(void)<br>
 {<br>
@@ -84,6 +84,7 @@ int suite_vm_tests_clean(void)<br>
 <br>
 CU_TestInfo vm_tests[] = {<br>
         { "resere vmid test",  amdgpu_vmid_reserve_test },<br>
+       { "vm mapping test",  amdgpu_vm_mapping_test },<br>
         CU_TEST_INFO_NULL,<br>
 };<br>
 <br>
@@ -167,3 +168,45 @@ static void amdgpu_vmid_reserve_test(void)<br>
         r = amdgpu_cs_ctx_free(context_handle);<br>
         CU_ASSERT_EQUAL(r, 0);<br>
 }<br>
+<br>
+static void amdgpu_vm_mapping_test(void)<br>
+{<br>
+       struct amdgpu_bo_alloc_request req = {0};<br>
+       struct drm_amdgpu_info_device dev_info;<br>
+       const uint64_t size = 4096;<br>
+       amdgpu_bo_handle buf;<br>
+       uint64_t addr;<br>
+       int r;<br>
+<br>
+       req.alloc_size = size;<br>
+       req.phys_alignment = 0;<br>
+       req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;<br>
+       req.flags = 0;<br>
+<br>
+       r = amdgpu_bo_alloc(device_handle, &req, &buf);<br>
+       CU_ASSERT_EQUAL(r, 0);<br>
+<br>
+       r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,<br>
+                             sizeof(dev_info), &dev_info);<br>
+       CU_ASSERT_EQUAL(r, 0);<br>
+<br>
+       addr = dev_info.virtual_address_offset;<br>
+       r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);<br>
+       CU_ASSERT_EQUAL(r, 0);<br>
+<br>
+       addr = dev_info.virtual_address_max - size;<br>
+       r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);<br>
+       CU_ASSERT_EQUAL(r, 0);<br>
+<br>
+       if (dev_info.high_va_offset) {<br>
+               addr = dev_info.high_va_offset;<br>
+               r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);<br>
+               CU_ASSERT_EQUAL(r, 0);<br>
+<br>
+               addr = dev_info.high_va_max - size;<br>
+               r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);<br>
+               CU_ASSERT_EQUAL(r, 0);<br>
+       }<br>
+<br>
+       amdgpu_bo_free(buf);<br>
+}<br>
-- <br>
2.17.1<br>
<br>
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