<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size: 12pt; color: rgb(0, 0, 0); font-family: Calibri, Helvetica, sans-serif, "EmojiFont", "Apple Color Emoji", "Segoe UI Emoji", NotoColorEmoji, "Segoe UI Symbol", "Android Emoji", EmojiSymbols;" dir="ltr"> <p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br> </p> <br> <br> <div style="color: rgb(0, 0, 0);"> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Yang, Philip <Philip.Yang@amd.com><br> <b>Sent:</b> Monday, November 12, 2018 2:20 PM<br> <b>To:</b> amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Yang, Philip<br> <b>Subject:</b> [PATCH] drm/amdgpu: fix bug with IH ring setup</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">The bug limits the IH ring wptr address to 40bit. When the system memory<br> is bigger than 1TB, the bus address is more than 40bit, this causes the<br> interrupt cannot be handled and cleared correctly.<br> <br> Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28<br> Signed-off-by: Philip Yang <Philip.Yang@amd.com><br> ---<br> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-<br> 1 file changed, 1 insertion(+), 1 deletion(-)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<br> index a99f717..a0fda6f 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<br> @@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)<br> else<br> wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);<br> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));<br> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);<br> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);<br> <br> /* set rptr, wptr to 0 */<br> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);<br> -- <br> 2.7.4<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" id="LPlnk129845" class="OWAAutoLink" previewremoved="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> </div> </span></font></div> </div> </div> </body> </html>