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<div class="moz-cite-prefix">Reviewed-by: Christian König
<a class="moz-txt-link-rfc2396E" href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a><br>
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Am 12.11.18 um 20:33 schrieb Deucher, Alexander:<br>
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<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex
Deucher <a class="moz-txt-link-rfc2396E" href="mailto:alexander.deucher@amd.com"><alexander.deucher@amd.com></a><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt"
face="Calibri, sans-serif" color="#000000"><b>From:</b>
amd-gfx <a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx-bounces@lists.freedesktop.org"><amd-gfx-bounces@lists.freedesktop.org></a> on
behalf of Yang, Philip <a class="moz-txt-link-rfc2396E" href="mailto:Philip.Yang@amd.com"><Philip.Yang@amd.com></a><br>
<b>Sent:</b> Monday, November 12, 2018 2:20 PM<br>
<b>To:</b> <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<b>Cc:</b> Yang, Philip<br>
<b>Subject:</b> [PATCH] drm/amdgpu: fix bug with IH ring
setup</font>
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<div class="PlainText">The bug limits the IH ring wptr
address to 40bit. When the system memory<br>
is bigger than 1TB, the bus address is more than
40bit, this causes the<br>
interrupt cannot be handled and cleared correctly.<br>
<br>
Change-Id: I3cd1b8ad046b38945372f2fd1a2d225624893e28<br>
Signed-off-by: Philip Yang <a class="moz-txt-link-rfc2396E" href="mailto:Philip.Yang@amd.com"><Philip.Yang@amd.com></a><br>
---<br>
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-<br>
1 file changed, 1 insertion(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<br>
index a99f717..a0fda6f 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<br>
@@ -129,7 +129,7 @@ static int
vega10_ih_irq_init(struct amdgpu_device *adev)<br>
else<br>
wptr_off = adev->wb.gpu_addr +
(adev->irq.ih.wptr_offs * 4);<br>
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
lower_32_bits(wptr_off));<br>
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
upper_32_bits(wptr_off) & 0xFF);<br>
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
upper_32_bits(wptr_off) & 0xFFFF);<br>
<br>
/* set rptr, wptr to 0 */<br>
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);<br>
-- <br>
2.7.4<br>
<br>
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<pre class="moz-quote-pre" wrap="">_______________________________________________
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