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<p style="margin-top:0;margin-bottom:0">Fwded.  You can also see the archives here:</p>
<p style="margin-top:0;margin-bottom:0"><a href="https://lists.freedesktop.org/archives/amd-gfx/2018-November/028781.html" class="OWAAutoLink" id="LPlnk948591" previewremoved="true">https://lists.freedesktop.org/archives/amd-gfx/2018-November/028781.html</a></p>
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<p style="margin-top:0;margin-bottom:0">Alex<br>
</p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zeng, Oak<br>
<b>Sent:</b> Friday, November 23, 2018 6:18:55 PM<br>
<b>To:</b> Deucher, Alexander; amd-gfx@lists.freedesktop.org<br>
<b>Subject:</b> RE: [PATCH] drm/amdgpu: Moved doorbell structures to seperate file</font>
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<p class="x_MsoNormal">Alex,</p>
<p class="x_MsoNormal"> </p>
<p class="x_MsoNormal">No I didnít. I donít know what happened to my email account.
</p>
<p class="x_MsoNormal"> </p>
<p class="x_MsoNormal">Can you forward that comment to me again?</p>
<p class="x_MsoNormal"> </p>
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<p class="x_MsoNormal">Regards,</p>
<p class="x_MsoNormal">Oak</p>
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<p class="x_MsoNormal"><b>From:</b> Deucher, Alexander <Alexander.Deucher@amd.com>
<br>
<b>Sent:</b> Friday, November 23, 2018 3:20 PM<br>
<b>To:</b> Zeng, Oak <Oak.Zeng@amd.com>; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zeng, Oak <Oak.Zeng@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu: Moved doorbell structures to seperate file</p>
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<p><span style="font-size:12.0pt; color:black">Did you see my other comments about consolidating vega10, raven, and vega12?</span></p>
<p><span style="font-size:12.0pt; color:black"> </span></p>
<p><span style="font-size:12.0pt; color:black">Reviewed-by: Alex Deucher <</span><a href="mailto:alexander.deucher@amd.com"><span style="font-size:12.0pt">alexander.deucher@amd.com</span></a><span style="font-size:12.0pt; color:black">></span></p>
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<p class="x_MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <</span><a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a><span style="color:black">> on behalf of Oak Zeng
 <</span><a href="mailto:ozeng@amd.com">ozeng@amd.com</a><span style="color:black">><br>
<b>Sent:</b> Friday, November 23, 2018 3:01:23 PM<br>
<b>To:</b> </span><a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><span style="color:black"><br>
<b>Cc:</b> Zeng, Oak<br>
<b>Subject:</b> [PATCH] drm/amdgpu: Moved doorbell structures to seperate file</span>
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<p class="x_MsoNormal">Move doorbell structures, enum definitions and helper functions<br>
from amdgpu.h to amdgpu_doorbell.h. No functional change<br>
<br>
Change-Id: I09f7b84869b6d3c688b7a2506ff78d62b3de23f5<br>
Signed-off-by: Oak Zeng <<a href="mailto:ozeng@amd.com">ozeng@amd.com</a>><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu.h          | 227 +-----------------------<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 249 +++++++++++++++++++++++++++<br>
 2 files changed, 250 insertions(+), 226 deletions(-)<br>
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
index e4101b1..7fc32c7 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
@@ -81,6 +81,7 @@<br>
 #include "amdgpu_job.h"<br>
 #include "amdgpu_bo_list.h"<br>
 #include "amdgpu_gem.h"<br>
+#include "amdgpu_doorbell.h"<br>
 <br>
 #define MAX_GPU_INSTANCE                16<br>
 <br>
@@ -361,173 +362,6 @@ int amdgpu_fence_slab_init(void);<br>
 void amdgpu_fence_slab_fini(void);<br>
 <br>
 /*<br>
- * GPU doorbell structures, functions & helpers<br>
- */<br>
-typedef enum _AMDGPU_DOORBELL_ASSIGNMENT<br>
-{<br>
-       AMDGPU_DOORBELL_KIQ                     = 0x000,<br>
-       AMDGPU_DOORBELL_HIQ                     = 0x001,<br>
-       AMDGPU_DOORBELL_DIQ                     = 0x002,<br>
-       AMDGPU_DOORBELL_MEC_RING0               = 0x010,<br>
-       AMDGPU_DOORBELL_MEC_RING1               = 0x011,<br>
-       AMDGPU_DOORBELL_MEC_RING2               = 0x012,<br>
-       AMDGPU_DOORBELL_MEC_RING3               = 0x013,<br>
-       AMDGPU_DOORBELL_MEC_RING4               = 0x014,<br>
-       AMDGPU_DOORBELL_MEC_RING5               = 0x015,<br>
-       AMDGPU_DOORBELL_MEC_RING6               = 0x016,<br>
-       AMDGPU_DOORBELL_MEC_RING7               = 0x017,<br>
-       AMDGPU_DOORBELL_GFX_RING0               = 0x020,<br>
-       AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,<br>
-       AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,<br>
-       AMDGPU_DOORBELL_IH                      = 0x1E8,<br>
-       AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,<br>
-       AMDGPU_DOORBELL_INVALID                 = 0xFFFF<br>
-} AMDGPU_DOORBELL_ASSIGNMENT;<br>
-<br>
-struct amdgpu_doorbell {<br>
-       /* doorbell mmio */<br>
-       resource_size_t         base;<br>
-       resource_size_t         size;<br>
-       u32 __iomem             *ptr;<br>
-       u32                     num_doorbells;  /* Number of doorbells actually reserved for amdgpu. */<br>
-};<br>
-<br>
-typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT<br>
-{<br>
-       /* Compute + GFX: 0~255 */<br>
-       AMDGPU_VEGA20_DOORBELL_KIQ                     = 0x000,<br>
-       AMDGPU_VEGA20_DOORBELL_HIQ                     = 0x001,<br>
-       AMDGPU_VEGA20_DOORBELL_DIQ                     = 0x002,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING0               = 0x003,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING1               = 0x004,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING2               = 0x005,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING3               = 0x006,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING4               = 0x007,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING5               = 0x008,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING6               = 0x009,<br>
-       AMDGPU_VEGA20_DOORBELL_MEC_RING7               = 0x00A,<br>
-       AMDGPU_VEGA20_DOORBELL_USERQUEUE_START         = 0x00B,<br>
-       AMDGPU_VEGA20_DOORBELL_USERQUEUE_END           = 0x08A,<br>
-       AMDGPU_VEGA20_DOORBELL_GFX_RING0               = 0x08B,<br>
-       /* SDMA:256~335*/<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0            = 0x100,<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1            = 0x10A,<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2            = 0x114,<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3            = 0x11E,<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4            = 0x128,<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5            = 0x132,<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6            = 0x13C,<br>
-       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7            = 0x146,<br>
-       /* IH: 376~391 */<br>
-       AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,<br>
-       /* MMSCH: 392~407<br>
-        * overlap the doorbell assignment with VCN as they are  mutually exclusive<br>
-        * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD<br>
-        */<br>
-       AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */<br>
-       AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,<br>
-       AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,<br>
-       AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,<br>
-<br>
-       AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,<br>
-       AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,<br>
-       AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,<br>
-       AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7             = 0x18B,<br>
-<br>
-       AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1             = 0x18C,<br>
-       AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3             = 0x18D,<br>
-       AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5             = 0x18E,<br>
-       AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7             = 0x18F,<br>
-       AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x18F,<br>
-       AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF<br>
-} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;<br>
-<br>
-/*<br>
- * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space<br>
- */<br>
-typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT<br>
-{<br>
-       /*<br>
-        * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in<br>
-        * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.<br>
-        *  Compute related doorbells are allocated from 0x00 to 0x8a<br>
-        */<br>
-<br>
-<br>
-       /* kernel scheduling */<br>
-       AMDGPU_DOORBELL64_KIQ                     = 0x00,<br>
-<br>
-       /* HSA interface queue and debug queue */<br>
-       AMDGPU_DOORBELL64_HIQ                     = 0x01,<br>
-       AMDGPU_DOORBELL64_DIQ                     = 0x02,<br>
-<br>
-       /* Compute engines */<br>
-       AMDGPU_DOORBELL64_MEC_RING0               = 0x03,<br>
-       AMDGPU_DOORBELL64_MEC_RING1               = 0x04,<br>
-       AMDGPU_DOORBELL64_MEC_RING2               = 0x05,<br>
-       AMDGPU_DOORBELL64_MEC_RING3               = 0x06,<br>
-       AMDGPU_DOORBELL64_MEC_RING4               = 0x07,<br>
-       AMDGPU_DOORBELL64_MEC_RING5               = 0x08,<br>
-       AMDGPU_DOORBELL64_MEC_RING6               = 0x09,<br>
-       AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,<br>
-<br>
-       /* User queue doorbell range (128 doorbells) */<br>
-       AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,<br>
-       AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,<br>
-<br>
-       /* Graphics engine */<br>
-       AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,<br>
-<br>
-       /*<br>
-        * Other graphics doorbells can be allocated here: from 0x8c to 0xdf<br>
-        * Graphics voltage island aperture 1<br>
-        * default non-graphics QWORD index is 0xe0 - 0xFF inclusive<br>
-        */<br>
-<br>
-       /* sDMA engines  reserved from 0xe0 -0xef  */<br>
-       AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xE0,<br>
-       AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xE1,<br>
-       AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,<br>
-       AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,<br>
-<br>
-       /* For vega10 sriov, the sdma doorbell must be fixed as follow<br>
-        * to keep the same setting with host driver, or it will<br>
-        * happen conflicts<br>
-        */<br>
-       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,<br>
-       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,<br>
-       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,<br>
-       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,<br>
-<br>
-       /* Interrupt handler */<br>
-       AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */<br>
-       AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */<br>
-       AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */<br>
-<br>
-       /* VCN engine use 32 bits doorbell  */<br>
-       AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */<br>
-       AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,<br>
-       AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,<br>
-       AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,<br>
-<br>
-       /* overlap the doorbell assignment with VCN as they are  mutually exclusive<br>
-        * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD<br>
-        */<br>
-       AMDGPU_DOORBELL64_UVD_RING0_1             = 0xF8,<br>
-       AMDGPU_DOORBELL64_UVD_RING2_3             = 0xF9,<br>
-       AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFA,<br>
-       AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFB,<br>
-<br>
-       AMDGPU_DOORBELL64_VCE_RING0_1             = 0xFC,<br>
-       AMDGPU_DOORBELL64_VCE_RING2_3             = 0xFD,<br>
-       AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,<br>
-       AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF,<br>
-<br>
-       AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,<br>
-       AMDGPU_DOORBELL64_INVALID                 = 0xFFFF<br>
-} AMDGPU_DOORBELL64_ASSIGNMENT;<br>
-<br>
-/*<br>
  * IRQS.<br>
  */<br>
 <br>
@@ -863,55 +697,6 @@ struct amd_powerplay {<br>
         uint32_t pp_feature;<br>
 };<br>
 <br>
-/* Reserved doorbells for amdgpu (including multimedia).<br>
- * KFD can use all the rest in the 2M doorbell bar.<br>
- * For asic before vega10, doorbell is 32-bit, so the<br>
- * index/offset is in dword. For vega10 and after, doorbell<br>
- * can be 64-bit, so the index defined is in qword.<br>
- */<br>
-struct amdgpu_doorbell_index {<br>
-       uint32_t kiq;<br>
-       uint32_t mec_ring0;<br>
-       uint32_t mec_ring1;<br>
-       uint32_t mec_ring2;<br>
-       uint32_t mec_ring3;<br>
-       uint32_t mec_ring4;<br>
-       uint32_t mec_ring5;<br>
-       uint32_t mec_ring6;<br>
-       uint32_t mec_ring7;<br>
-       uint32_t userqueue_start;<br>
-       uint32_t userqueue_end;<br>
-       uint32_t gfx_ring0;<br>
-       uint32_t sdma_engine0;<br>
-       uint32_t sdma_engine1;<br>
-       uint32_t sdma_engine2;<br>
-       uint32_t sdma_engine3;<br>
-       uint32_t sdma_engine4;<br>
-       uint32_t sdma_engine5;<br>
-       uint32_t sdma_engine6;<br>
-       uint32_t sdma_engine7;<br>
-       uint32_t ih;<br>
-       union {<br>
-               struct {<br>
-                       uint32_t vcn_ring0_1;<br>
-                       uint32_t vcn_ring2_3;<br>
-                       uint32_t vcn_ring4_5;<br>
-                       uint32_t vcn_ring6_7;<br>
-               } vcn;<br>
-               struct {<br>
-                       uint32_t uvd_ring0_1;<br>
-                       uint32_t uvd_ring2_3;<br>
-                       uint32_t uvd_ring4_5;<br>
-                       uint32_t uvd_ring6_7;<br>
-                       uint32_t vce_ring0_1;<br>
-                       uint32_t vce_ring2_3;<br>
-                       uint32_t vce_ring4_5;<br>
-                       uint32_t vce_ring6_7;<br>
-               } uvd_vce;<br>
-       };<br>
-       uint32_t max_assignment;<br>
-};<br>
-<br>
 #define AMDGPU_RESET_MAGIC_NUM 64<br>
 struct amdgpu_device {<br>
         struct device                   *dev;<br>
@@ -1150,11 +935,6 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);<br>
 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);<br>
 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);<br>
 <br>
-u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);<br>
-void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);<br>
-u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);<br>
-void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);<br>
-<br>
 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);<br>
 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);<br>
 <br>
@@ -1216,11 +996,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);<br>
 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))<br>
 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))<br>
 <br>
-#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))<br>
-#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))<br>
-#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))<br>
-#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))<br>
-<br>
 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT<br>
 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK<br>
 <br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h<br>
new file mode 100644<br>
index 0000000..708ac73<br>
--- /dev/null<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h<br>
@@ -0,0 +1,249 @@<br>
+/*<br>
+ * Copyright 2018 Advanced Micro Devices, Inc.<br>
+ *<br>
+ * Permission is hereby granted, free of charge, to any person obtaining a<br>
+ * copy of this software and associated documentation files (the "Software"),<br>
+ * to deal in the Software without restriction, including without limitation<br>
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,<br>
+ * and/or sell copies of the Software, and to permit persons to whom the<br>
+ * Software is furnished to do so, subject to the following conditions:<br>
+ *<br>
+ * The above copyright notice and this permission notice shall be included in<br>
+ * all copies or substantial portions of the Software.<br>
+ *<br>
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR<br>
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,<br>
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL<br>
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR<br>
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,<br>
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR<br>
+ * OTHER DEALINGS IN THE SOFTWARE.<br>
+ *<br>
+ */<br>
+<br>
+/*<br>
+ * GPU doorbell structures, functions & helpers<br>
+ */<br>
+struct amdgpu_doorbell {<br>
+       /* doorbell mmio */<br>
+       resource_size_t         base;<br>
+       resource_size_t         size;<br>
+       u32 __iomem             *ptr;<br>
+       u32                     num_doorbells;  /* Number of doorbells actually reserved for amdgpu. */<br>
+};<br>
+<br>
+/* Reserved doorbells for amdgpu (including multimedia).<br>
+ * KFD can use all the rest in the 2M doorbell bar.<br>
+ * For asic before vega10, doorbell is 32-bit, so the<br>
+ * index/offset is in dword. For vega10 and after, doorbell<br>
+ * can be 64-bit, so the index defined is in qword.<br>
+ */<br>
+struct amdgpu_doorbell_index {<br>
+       uint32_t kiq;<br>
+       uint32_t mec_ring0;<br>
+       uint32_t mec_ring1;<br>
+       uint32_t mec_ring2;<br>
+       uint32_t mec_ring3;<br>
+       uint32_t mec_ring4;<br>
+       uint32_t mec_ring5;<br>
+       uint32_t mec_ring6;<br>
+       uint32_t mec_ring7;<br>
+       uint32_t userqueue_start;<br>
+       uint32_t userqueue_end;<br>
+       uint32_t gfx_ring0;<br>
+       uint32_t sdma_engine0;<br>
+       uint32_t sdma_engine1;<br>
+       uint32_t sdma_engine2;<br>
+       uint32_t sdma_engine3;<br>
+       uint32_t sdma_engine4;<br>
+       uint32_t sdma_engine5;<br>
+       uint32_t sdma_engine6;<br>
+       uint32_t sdma_engine7;<br>
+       uint32_t ih;<br>
+       union {<br>
+               struct {<br>
+                       uint32_t vcn_ring0_1;<br>
+                       uint32_t vcn_ring2_3;<br>
+                       uint32_t vcn_ring4_5;<br>
+                       uint32_t vcn_ring6_7;<br>
+               } vcn;<br>
+               struct {<br>
+                       uint32_t uvd_ring0_1;<br>
+                       uint32_t uvd_ring2_3;<br>
+                       uint32_t uvd_ring4_5;<br>
+                       uint32_t uvd_ring6_7;<br>
+                       uint32_t vce_ring0_1;<br>
+                       uint32_t vce_ring2_3;<br>
+                       uint32_t vce_ring4_5;<br>
+                       uint32_t vce_ring6_7;<br>
+               } uvd_vce;<br>
+       };<br>
+       uint32_t max_assignment;<br>
+};<br>
+<br>
+typedef enum _AMDGPU_DOORBELL_ASSIGNMENT<br>
+{<br>
+       AMDGPU_DOORBELL_KIQ                     = 0x000,<br>
+       AMDGPU_DOORBELL_HIQ                     = 0x001,<br>
+       AMDGPU_DOORBELL_DIQ                     = 0x002,<br>
+       AMDGPU_DOORBELL_MEC_RING0               = 0x010,<br>
+       AMDGPU_DOORBELL_MEC_RING1               = 0x011,<br>
+       AMDGPU_DOORBELL_MEC_RING2               = 0x012,<br>
+       AMDGPU_DOORBELL_MEC_RING3               = 0x013,<br>
+       AMDGPU_DOORBELL_MEC_RING4               = 0x014,<br>
+       AMDGPU_DOORBELL_MEC_RING5               = 0x015,<br>
+       AMDGPU_DOORBELL_MEC_RING6               = 0x016,<br>
+       AMDGPU_DOORBELL_MEC_RING7               = 0x017,<br>
+       AMDGPU_DOORBELL_GFX_RING0               = 0x020,<br>
+       AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,<br>
+       AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,<br>
+       AMDGPU_DOORBELL_IH                      = 0x1E8,<br>
+       AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,<br>
+       AMDGPU_DOORBELL_INVALID                 = 0xFFFF<br>
+} AMDGPU_DOORBELL_ASSIGNMENT;<br>
+<br>
+typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT<br>
+{<br>
+       /* Compute + GFX: 0~255 */<br>
+       AMDGPU_VEGA20_DOORBELL_KIQ                     = 0x000,<br>
+       AMDGPU_VEGA20_DOORBELL_HIQ                     = 0x001,<br>
+       AMDGPU_VEGA20_DOORBELL_DIQ                     = 0x002,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING0               = 0x003,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING1               = 0x004,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING2               = 0x005,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING3               = 0x006,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING4               = 0x007,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING5               = 0x008,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING6               = 0x009,<br>
+       AMDGPU_VEGA20_DOORBELL_MEC_RING7               = 0x00A,<br>
+       AMDGPU_VEGA20_DOORBELL_USERQUEUE_START         = 0x00B,<br>
+       AMDGPU_VEGA20_DOORBELL_USERQUEUE_END           = 0x08A,<br>
+       AMDGPU_VEGA20_DOORBELL_GFX_RING0               = 0x08B,<br>
+       /* SDMA:256~335*/<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0            = 0x100,<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1            = 0x10A,<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2            = 0x114,<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3            = 0x11E,<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4            = 0x128,<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5            = 0x132,<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6            = 0x13C,<br>
+       AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7            = 0x146,<br>
+       /* IH: 376~391 */<br>
+       AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,<br>
+       /* MMSCH: 392~407<br>
+        * overlap the doorbell assignment with VCN as they are  mutually exclusive<br>
+        * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD<br>
+        */<br>
+       AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */<br>
+       AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,<br>
+       AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,<br>
+       AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,<br>
+<br>
+       AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,<br>
+       AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,<br>
+       AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,<br>
+       AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7             = 0x18B,<br>
+<br>
+       AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1             = 0x18C,<br>
+       AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3             = 0x18D,<br>
+       AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5             = 0x18E,<br>
+       AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7             = 0x18F,<br>
+       AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT            = 0x18F,<br>
+       AMDGPU_VEGA20_DOORBELL_INVALID                   = 0xFFFF<br>
+} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;<br>
+<br>
+/*<br>
+ * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space<br>
+ */<br>
+typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT<br>
+{<br>
+       /*<br>
+        * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in<br>
+        * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.<br>
+        *  Compute related doorbells are allocated from 0x00 to 0x8a<br>
+        */<br>
+<br>
+<br>
+       /* kernel scheduling */<br>
+       AMDGPU_DOORBELL64_KIQ                     = 0x00,<br>
+<br>
+       /* HSA interface queue and debug queue */<br>
+       AMDGPU_DOORBELL64_HIQ                     = 0x01,<br>
+       AMDGPU_DOORBELL64_DIQ                     = 0x02,<br>
+<br>
+       /* Compute engines */<br>
+       AMDGPU_DOORBELL64_MEC_RING0               = 0x03,<br>
+       AMDGPU_DOORBELL64_MEC_RING1               = 0x04,<br>
+       AMDGPU_DOORBELL64_MEC_RING2               = 0x05,<br>
+       AMDGPU_DOORBELL64_MEC_RING3               = 0x06,<br>
+       AMDGPU_DOORBELL64_MEC_RING4               = 0x07,<br>
+       AMDGPU_DOORBELL64_MEC_RING5               = 0x08,<br>
+       AMDGPU_DOORBELL64_MEC_RING6               = 0x09,<br>
+       AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,<br>
+<br>
+       /* User queue doorbell range (128 doorbells) */<br>
+       AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,<br>
+       AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,<br>
+<br>
+       /* Graphics engine */<br>
+       AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,<br>
+<br>
+       /*<br>
+        * Other graphics doorbells can be allocated here: from 0x8c to 0xdf<br>
+        * Graphics voltage island aperture 1<br>
+        * default non-graphics QWORD index is 0xe0 - 0xFF inclusive<br>
+        */<br>
+<br>
+       /* sDMA engines  reserved from 0xe0 -0xef  */<br>
+       AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xE0,<br>
+       AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xE1,<br>
+       AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,<br>
+       AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9,<br>
+<br>
+       /* For vega10 sriov, the sdma doorbell must be fixed as follow<br>
+        * to keep the same setting with host driver, or it will<br>
+        * happen conflicts<br>
+        */<br>
+       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,<br>
+       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,<br>
+       AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,<br>
+       AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,<br>
+<br>
+       /* Interrupt handler */<br>
+       AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */<br>
+       AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */<br>
+       AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */<br>
+<br>
+       /* VCN engine use 32 bits doorbell  */<br>
+       AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */<br>
+       AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,<br>
+       AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,<br>
+       AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,<br>
+<br>
+       /* overlap the doorbell assignment with VCN as they are  mutually exclusive<br>
+        * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD<br>
+        */<br>
+       AMDGPU_DOORBELL64_UVD_RING0_1             = 0xF8,<br>
+       AMDGPU_DOORBELL64_UVD_RING2_3             = 0xF9,<br>
+       AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFA,<br>
+       AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFB,<br>
+<br>
+       AMDGPU_DOORBELL64_VCE_RING0_1             = 0xFC,<br>
+       AMDGPU_DOORBELL64_VCE_RING2_3             = 0xFD,<br>
+       AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,<br>
+       AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF,<br>
+<br>
+       AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,<br>
+       AMDGPU_DOORBELL64_INVALID                 = 0xFFFF<br>
+} AMDGPU_DOORBELL64_ASSIGNMENT;<br>
+<br>
+u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);<br>
+void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);<br>
+u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);<br>
+void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);<br>
+<br>
+#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))<br>
+#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))<br>
+#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))<br>
+#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))<br>
+<br>
-- <br>
2.7.4<br>
<br>
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