<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> </head> <body text="#000000" bgcolor="#FFFFFF"> On 11/24/18 3:32 AM, Deucher, Alexander wrote: <blockquote type="cite" cite="mid:BN6PR12MB18091B4409C1DC5CD17F903CF7D40@BN6PR12MB1809.namprd12.prod.outlook.com"> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> <style type="text/css" style="display:none;"></style> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> Is this required? Are the harvesting fuses incorrect? If the blocks are harvested, we should bail out of the blocks properly during init. Also, please make this more explicit if we still need it. E.g., </div> </blockquote> The harvest fuse is indeed disabling UVD and VCE, as it's a mining card. Then any command to UVD/VCE causing NULL pointer issue, like amdgpu_test. AFAIW, windows also disable UVD and VCE in initialization. <blockquote type="cite" cite="mid:BN6PR12MB18091B4409C1DC5CD17F903CF7D40@BN6PR12MB1809.namprd12.prod.outlook.com"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> if ((adev->pdev->device == 0x67df) && (adev->pdev->revision == 0xf7)) { /* Some polaris12 variants don't support UVD/VCE */ } else { amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); } </div> </blockquote> OK, will explicit the process. Regards, Jerry <blockquote type="cite" cite="mid:BN6PR12MB18091B4409C1DC5CD17F903CF7D40@BN6PR12MB1809.namprd12.prod.outlook.com"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> That way if we re-arrange the order later, it will be easier to track. Alex </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">From: amd-gfx <a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx-bounces@lists.freedesktop.org"><amd-gfx-bounces@lists.freedesktop.org></a> on behalf of Junwei Zhang <a class="moz-txt-link-rfc2396E" href="mailto:Jerry.Zhang@amd.com"><Jerry.Zhang@amd.com></a> Sent: Friday, November 23, 2018 3:32:27 AM To: <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> Cc: Zhang, Jerry Subject: [PATCH] drm/amdgpu: disable UVD/VCE for some polaris 12 variants <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">Some variants don't support UVD and VCE. Signed-off-by: Junwei Zhang <a class="moz-txt-link-rfc2396E" href="mailto:Jerry.Zhang@amd.com"><Jerry.Zhang@amd.com></a> --- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index f3a4cf1f013a..3338b013ded4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1660,6 +1660,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); + /* Some polaris12 variants don't support UVD/VCE */ + if ((adev->pdev->device == 0x67df) && + (adev->pdev->revision == 0xf7)) + break; amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); break; -- 2.17.1 _______________________________________________ amd-gfx mailing list <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" moz-do-not-send="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a> </div> </div> </blockquote> </body> </html>