<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta content="text/html; charset=us-ascii"> <style type="text/css" style="display:none">  </style> </head> <body dir="ltr"> <div dir="auto" style="direction:ltr; margin:0; padding:0; font-family:sans-serif; font-size:11pt; color:black"> This is for the devices with type-c ports.<br> <br> </div> <div dir="auto" style="direction:ltr; margin:0; padding:0; font-family:sans-serif; font-size:11pt; color:black"> Wherein the signal type is same 32 (DISPLAY PORT) for both HDMI and DP monitors connected to the system via type-c dongles/convertors.<br> <br> </div> <div dir="auto" style="direction:ltr; margin:0; padding:0; font-family:sans-serif; font-size:11pt; color:black"> Regards,<br> </div> <div dir="auto" style="direction:ltr; margin:0; padding:0; font-family:sans-serif; font-size:11pt; color:black"> Shirish S<br> <br> </div> <div dir="auto" style="direction:ltr; margin:0; padding:0; font-family:sans-serif; font-size:11pt; color:black"> <div dir="auto" style="direction:ltr; margin:0; padding:0; font-family:sans-serif; font-size:11pt; color:black"> Get <a href="https://aka.ms/ghei36">Outlook for Android</a></div> <br> </div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Deucher, Alexander<br> <b>Sent:</b> Wednesday, November 28, 2018 12:06:26 AM<br> <b>To:</b> S, Shirish; Li, Sun peng (Leo); Wentland, Harry<br> <b>Cc:</b> amd-gfx@lists.freedesktop.org<br> <b>Subject:</b> Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ</font> <div> </div> </div> <div> <div id="divtagdefaultwrapper" dir="ltr" style="font-size:12pt; color:#000000; font-family:Calibri,Helvetica,sans-serif"> <p style="margin-top:0; margin-bottom:0">Is this a DP to HDMI adapter? I think 4k@60 should be valid on DP in general on ST/CZ, but Harry or Leo should comment.</p> <p style="margin-top:0; margin-bottom:0"><br> </p> <p style="margin-top:0; margin-bottom:0">Alex<br> </p> </div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> S, Shirish<br> <b>Sent:</b> Tuesday, November 27, 2018 3:58:12 AM<br> <b>To:</b> Deucher, Alexander; Li, Sun peng (Leo); Wentland, Harry<br> <b>Cc:</b> amd-gfx@lists.freedesktop.org<br> <b>Subject:</b> RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ</font> <div> </div> </div> <style>  </style> <div lang="EN-US"> <div class="x_WordSection1"> <p class="x_MsoNormal">However, while using Type-C connectors noted that the signal type is actually SIGNAL_TYPE_DISPLAY_PORT and found that the check was missing.</p> <p class="x_MsoNormal">Hence have added the same in <a href="https://patchwork.freedesktop.org/patch/264033/"> https://patchwork.freedesktop.org/patch/264033/</a></p> <div> <p class="x_MsoNormal"> </p> <p class="x_MsoNormal">Regards,</p> <p class="x_MsoNormal">Shirish S</p> </div> <p class="x_MsoNormal"> </p> <div> <div style="border:none; border-top:solid #E1E1E1 1.0pt; padding:3.0pt 0in 0in 0in"> <p class="x_MsoNormal"><b>From:</b> S, Shirish <br> <b>Sent:</b> Tuesday, November 27, 2018 9:54 AM<br> <b>To:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com><br> <b>Cc:</b> amd-gfx@lists.freedesktop.org<br> <b>Subject:</b> RE: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ</p> </div> </div> <p class="x_MsoNormal"> </p> <p class="x_MsoNormal">Thanks Alex, found that patch.</p> <p class="x_MsoNormal">My patch is no more required.</p> <div> <p class="x_MsoNormal"> </p> <p class="x_MsoNormal"> </p> <p class="x_MsoNormal">Regards,</p> <p class="x_MsoNormal">Shirish S</p> </div> <p class="x_MsoNormal"> </p> <div> <div style="border:none; border-top:solid #E1E1E1 1.0pt; padding:3.0pt 0in 0in 0in"> <p class="x_MsoNormal"><b>From:</b> Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>> <br> <b>Sent:</b> Monday, November 26, 2018 7:46 PM<br> <b>To:</b> S, Shirish <<a href="mailto:Shirish.S@amd.com">Shirish.S@amd.com</a>>; Li, Sun peng (Leo) <<a href="mailto:Sunpeng.Li@amd.com">Sunpeng.Li@amd.com</a>>; Wentland, Harry <<a href="mailto:Harry.Wentland@amd.com">Harry.Wentland@amd.com</a>><br> <b>Cc:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> <b>Subject:</b> Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ</p> </div> </div> <p class="x_MsoNormal"> </p> <div id="x_divtagdefaultwrapper"> <p><span style="font-size:12.0pt; color:black">I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?</span></p> <p><span style="font-size:12.0pt; color:black"> </span></p> <p><span style="font-size:12.0pt; color:black">Alex</span></p> </div> <div class="x_MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="x_divRplyFwdMsg"> <p class="x_MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of S, Shirish <<a href="mailto:Shirish.S@amd.com">Shirish.S@amd.com</a>><br> <b>Sent:</b> Monday, November 26, 2018 1:36:30 AM<br> <b>To:</b> Li, Sun peng (Leo); Wentland, Harry<br> <b>Cc:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>; S, Shirish<br> <b>Subject:</b> [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ</span> </p> <div> <p class="x_MsoNormal"> </p> </div> </div> <div> <div> <p class="x_MsoNormal">[Why]<br> ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,<br> that it cannot handle correctly, hence resulting in<br> several issues like flickering, black lines/flashes and so on.<br> <br> [How]<br> These modes are basically high pixel clock ones, hence<br> limit the same to be advertised to avoid bad user experiences<br> <br> Signed-off-by: Shirish S <<a href="mailto:shirish.s@amd.com">shirish.s@amd.com</a>><br> Suggested-by: Harry Wentland <<a href="mailto:harry.wentland@amd.com">harry.wentland@amd.com</a>><br> ---<br> .../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++<br> 1 file changed, 10 insertions(+)<br> <br> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c<br> index 1b2fe0d..1b8fe99 100644<br> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c<br> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c<br> @@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(<br> if (!timing)<br> return false;<br> <br> + /* Limit all modes that have a high pixel clock<br> + * which seems to be problematic on dce110<br> + * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz<br> + * based on the below formula:<br> + * refresh rate = pixel clock / (htotal * vtotal)<br> + */<br> + if (timing->pix_clk_khz > 300000)<br> + return false;<br> +<br> +<br> hsync_offset = timing->h_border_right + timing->h_front_porch;<br> h_sync_start = timing->h_addressable + hsync_offset;<br> <br> -- <br> 2.7.4<br> <br> _______________________________________________<br> amd-gfx mailing list<br> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a></p> </div> </div> </div> </div> </div> </body> </html>