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<p class="MsoNormal">Thanks Alex, found that patch.<o:p></o:p></p>
<p class="MsoNormal">My patch is no more required.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Shirish S<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Deucher, Alexander <Alexander.Deucher@amd.com> <br>
<b>Sent:</b> Monday, November 26, 2018 7:46 PM<br>
<b>To:</b> S, Shirish <Shirish.S@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com><br>
<b>Cc:</b> amd-gfx@lists.freedesktop.org<br>
<b>Subject:</b> Re: [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p><span style="font-size:12.0pt;color:black">I thought there was a patch to do this already that got sent out a few weeks ago. Basically limit ST/CZ to modes that do not require a retimer. Is an additional patch needed?<o:p></o:p></span></p>
<p><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p>
<p><span style="font-size:12.0pt;color:black">Alex<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of S, Shirish <<a href="mailto:Shirish.S@amd.com">Shirish.S@amd.com</a>><br>
<b>Sent:</b> Monday, November 26, 2018 1:36:30 AM<br>
<b>To:</b> Li, Sun peng (Leo); Wentland, Harry<br>
<b>Cc:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>; S, Shirish<br>
<b>Subject:</b> [PATCH] drm/amd/display: limit high pixel clock modes on ST/CZ</span>
<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">[Why]<br>
ST/CZ (dce110) advertises modes such as 4k@60Hz etc.,<br>
that it cannot handle correctly, hence resulting in<br>
several issues like flickering, black lines/flashes and so on.<br>
<br>
[How]<br>
These modes are basically high pixel clock ones, hence<br>
limit the same to be advertised to avoid bad user experiences<br>
<br>
Signed-off-by: Shirish S <<a href="mailto:shirish.s@amd.com">shirish.s@amd.com</a>><br>
Suggested-by: Harry Wentland <<a href="mailto:harry.wentland@amd.com">harry.wentland@amd.com</a>><br>
---<br>
.../gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 10 ++++++++++<br>
1 file changed, 10 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c<br>
index 1b2fe0d..1b8fe99 100644<br>
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c<br>
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c<br>
@@ -1121,6 +1121,16 @@ bool dce110_timing_generator_validate_timing(<br>
if (!timing)<br>
return false;<br>
<br>
+ /* Limit all modes that have a high pixel clock<br>
+ * which seems to be problematic on dce110<br>
+ * These include: 4k@60Hz, 1080p@144Hz,1440p@120Hz<br>
+ * based on the below formula:<br>
+ * refresh rate = pixel clock / (htotal * vtotal)<br>
+ */<br>
+ if (timing->pix_clk_khz > 300000)<br>
+ return false;<br>
+<br>
+<br>
hsync_offset = timing->h_border_right + timing->h_front_porch;<br>
h_sync_start = timing->h_addressable + hsync_offset;<br>
<br>
-- <br>
2.7.4<br>
<br>
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