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<p>With this change in latest drm-next and related commit in latest FW i get <br>
</p>
<p><br>
</p>
<p>[  148.887374] [drm:psp_hw_init [amdgpu]] *ERROR* PSP firmware loading failed<br>
[  148.887535] [drm:amdgpu_device_fw_loading [amdgpu]] *ERROR* hw_init of IP block <psp> failed -22<br>
</p>
<p><br>
</p>
<p>Had to revert to be able to boot.</p>
<p><br>
</p>
<p>Andrey<br>
</p>
<br>
<div class="moz-cite-prefix">On 12/13/2018 10:05 AM, Deucher, Alexander wrote:<br>
</div>
<blockquote type="cite" cite="mid:BN6PR12MB180900FC993E80DD7F22127AF7A00@BN6PR12MB1809.namprd12.prod.outlook.com">
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<p style="margin-top:0;margin-bottom:0">Acked-by: Alex Deucher <a class="moz-txt-link-rfc2396E" href="mailto:alexander.deucher@amd.com">
<alexander.deucher@amd.com></a><br>
</p>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx
<a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx-bounces@lists.freedesktop.org">
<amd-gfx-bounces@lists.freedesktop.org></a> on behalf of Evan Quan <a class="moz-txt-link-rfc2396E" href="mailto:evan.quan@amd.com">
<evan.quan@amd.com></a><br>
<b>Sent:</b> Thursday, December 13, 2018 1:14:51 AM<br>
<b>To:</b> <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">
amd-gfx@lists.freedesktop.org</a><br>
<b>Cc:</b> Quan, Evan<br>
<b>Subject:</b> [PATCH] drm/amdgpu: unify Vega20 PSP SOS firmwares for A0 and A1</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">The new PSP SOS firmware can support both A0 and A1.<br>
<br>
Change-Id: I9bf85eb77b183a4403667c77e291e32689aed0af<br>
---<br>
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 +-----------<br>
 1 file changed, 1 insertion(+), 11 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c<br>
index 61cf2f6954e7..f3f5d4dd4631 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c<br>
@@ -34,14 +34,11 @@<br>
 #include "nbio/nbio_7_4_offset.h"<br>
 <br>
 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");<br>
-MODULE_FIRMWARE("amdgpu/vega20_sos_old.bin");<br>
 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");<br>
 <br>
 /* address block */<br>
 #define smnMP1_FIRMWARE_FLAGS           0x3010024<br>
 <br>
-#define VEGA20_BL_VERSION_VAR_NEW 0xA1<br>
-<br>
 static int<br>
 psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)<br>
 {<br>
@@ -104,7 +101,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)<br>
         int err = 0;<br>
         const struct psp_firmware_header_v1_0 *sos_hdr;<br>
         const struct ta_firmware_header_v1_0 *ta_hdr;<br>
-       uint32_t bl_version;<br>
 <br>
         DRM_DEBUG("\n");<br>
 <br>
@@ -116,13 +112,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)<br>
                 BUG();<br>
         }<br>
 <br>
-       bl_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_100);<br>
-       bl_version = (bl_version & 0xFF0000) >> 16;<br>
-<br>
-       if (bl_version == VEGA20_BL_VERSION_VAR_NEW)<br>
-               snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);<br>
-       else<br>
-               snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos_old.bin", chip_name);<br>
+       snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);<br>
         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);<br>
         if (err)<br>
                 goto out;<br>
-- <br>
2.19.2<br>
<br>
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