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<div class="moz-cite-prefix">Hi Wentao,<br>
<br>
well the problem is you don't seem to understand how the hardware works.<br>
<br>
See the engines see an MC address space with a hole in the middle, similar to the how x86 64bit CPU address space works. But the page tables are programmed linearly.<br>
<br>
So the calculation in amdgpu_driver_open_kms() is correct because it takes the MC address and mages a linear page table index from it again.<br>
<br>
The only thing we might need to fix here is shifting max_pfn before the subtraction and I doubt that even that is necessary.<br>
<br>
Regards,<br>
Christian.<br>
<br>
Am 16.01.19 um 10:34 schrieb Lou, Wentao:<br>
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<p class="MsoPlainText">Hi Christian,<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Now vm_size was set to <span style="background:yellow;mso-highlight:yellow">
0x4 0000</span> GB by below commit:<o:p></o:p></p>
<p class="MsoPlainText">1bf621c42137926ac249af761c0190a9258aa0db drm/amdgpu: Remove unnecessary VM size calculations<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">So that max_pfn would be <span style="background:yellow;mso-highlight:yellow">
0x10 0000 0000.<o:p></o:p></span></p>
<p class="MsoPlainText">amdgpu_csa_vaddr would make max_pfn << 12 to get 0x1 0000 0000 0000, and then minus AMDGPU_VA_RESERVED_SIZE, to get
<span style="background:yellow;mso-highlight:yellow">0xFFFF FFF0 0000</span><o:p></o:p></p>
<p class="MsoPlainText">unfortunately this number was between AMDGPU_GMC_HOLE_START and AMDGPU_GMC_HOLE_END, so that amdgpu_gmc_sign_extend was called to make it
<span style="background:yellow;mso-highlight:yellow">0xFFFF FFFF FFF0 0000</span><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">in amdgpu_driver_open_kms, extended csa_addr cannot be passed into amdgpu_map_static_csa directly, it would be above the limit of max_pfn.<o:p></o:p></p>
<p class="MsoPlainText">So that csa_addr was restricted by AMDGPU_GMC_HOLE_MASK to make it possible for amdgpu_vm_alloc_pts.<o:p></o:p></p>
<p class="MsoPlainText">But this restriction by AMDGPU_GMC_HOLE_MASK would make the address fall back into AMDGPU_GMC_HOLE again, which causing GPU reset.<o:p></o:p></p>
<p class="MsoPlainText">We just put amdgpu_csa_vaddr back to AMDGPU_GMC_HOLE_START, to avoid the address touching AMDGPU_GMC_HOLE.<o:p></o:p></p>
<p class="MsoPlainText">By the way, if max_pfn was shift much to the left, it would always get zero, with or without min(*,*).<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">BR,<o:p></o:p></p>
<p class="MsoPlainText">Wentao<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">-----Original Message-----<br>
From: Koenig, Christian <a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com">
<Christian.Koenig@amd.com></a> <br>
Sent: Tuesday, January 15, 2019 4:02 PM<br>
To: Liu, Monk <a class="moz-txt-link-rfc2396E" href="mailto:Monk.Liu@amd.com"><Monk.Liu@amd.com></a>; Lou, Wentao
<a class="moz-txt-link-rfc2396E" href="mailto:Wentao.Lou@amd.com"><Wentao.Lou@amd.com></a>;
<a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>; Zhu, Rex
<a class="moz-txt-link-rfc2396E" href="mailto:Rex.Zhu@amd.com"><Rex.Zhu@amd.com></a><br>
Subject: Re: [PATCH] drm/amdgpu: csa_vaddr should not larger than AMDGPU_GMC_HOLE_START</p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Am 15.01.19 um 07:19 schrieb Liu, Monk:<o:p></o:p></p>
<p class="MsoPlainText">> The max_pfn is now 1'0000'0000'0000'0000 (bytes) which is above 48 bit now, and it with AMDGPU_GMC_HOLE_MASK make it to zero ....<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> And in code "amdgpu_driver_open_kms()" I saw @Zhu, Rex write the code as :<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> "csa_addr = amdgpu_csa_vadr(adev) & AMDGPU_GMC_HOLE_MASK", I think this is wrong since you intentionally place the csa above GMC hole, right ?<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">The fix is just completely incorrect since min(adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT, AMDGPU_GMC_HOLE_START) still gives you 0 when we shift max_pfn to much to the left.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">The correct solution is to substract the reserved size first and then shift. E.g.:<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">addr = (max_pfn - (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_PAGE_SHIFT)) << AMDGPU_PAGE_SHIFT;<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Regards,<o:p></o:p></p>
<p class="MsoPlainText">Christian.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Looks like we should modify this place<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> /Monk<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> -----Original Message-----<o:p></o:p></p>
<p class="MsoPlainText">> From: amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org" moz-do-not-send="true"><span style="text-decoration:none">amd-gfx-bounces@lists.freedesktop.org</span></a>> On Behalf Of
<o:p></o:p></p>
<p class="MsoPlainText">> Christian K?nig<o:p></o:p></p>
<p class="MsoPlainText">> Sent: Monday, January 14, 2019 9:05 PM<o:p></o:p></p>
<p class="MsoPlainText">> To: Lou, Wentao <<a href="mailto:Wentao.Lou@amd.com" moz-do-not-send="true"><span style="text-decoration:none">Wentao.Lou@amd.com</span></a>>;
<a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true"><span style="text-decoration:none">amd-gfx@lists.freedesktop.org</span></a><o:p></o:p></p>
<p class="MsoPlainText">> Subject: Re: [PATCH] drm/amdgpu: csa_vaddr should not larger than
<o:p></o:p></p>
<p class="MsoPlainText">> AMDGPU_GMC_HOLE_START<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Am 14.01.19 um 09:40 schrieb wentalou:<o:p></o:p></p>
<p class="MsoPlainText">>> After removing unnecessary VM size calculations, vm_manager.max_pfn
<o:p></o:p></p>
<p class="MsoPlainText">>> would reach 0x10,0000,0000 max_pfn << AMDGPU_GPU_PAGE_SHIFT exceeding
<o:p></o:p></p>
<p class="MsoPlainText">>> AMDGPU_GMC_HOLE_START would caused GPU reset.<o:p></o:p></p>
<p class="MsoPlainText">>><o:p> </o:p></p>
<p class="MsoPlainText">>> Change-Id: I47ad0be2b0bd9fb7490c4e1d7bb7bdacf71132cb<o:p></o:p></p>
<p class="MsoPlainText">>> Signed-off-by: wentalou <<a href="mailto:Wentao.Lou@amd.com" moz-do-not-send="true"><span style="text-decoration:none">Wentao.Lou@amd.com</span></a>><o:p></o:p></p>
<p class="MsoPlainText">> NAK, that is incorrect. We intentionally place the csa above the GMC hole.<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Regards,<o:p></o:p></p>
<p class="MsoPlainText">> Christian.<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">>> ---<o:p></o:p></p>
<p class="MsoPlainText">>> drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 3 ++-<o:p></o:p></p>
<p class="MsoPlainText">>> 1 file changed, 2 insertions(+), 1 deletion(-)<o:p></o:p></p>
<p class="MsoPlainText">>><o:p> </o:p></p>
<p class="MsoPlainText">>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c<o:p></o:p></p>
<p class="MsoPlainText">>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c<o:p></o:p></p>
<p class="MsoPlainText">>> index 7e22be7..dd3bd01 100644<o:p></o:p></p>
<p class="MsoPlainText">>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c<o:p></o:p></p>
<p class="MsoPlainText">>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c<o:p></o:p></p>
<p class="MsoPlainText">>> @@ -26,7 +26,8 @@<o:p></o:p></p>
<p class="MsoPlainText">>> <o:p></o:p></p>
<p class="MsoPlainText">>> uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)<o:p></o:p></p>
<p class="MsoPlainText">>> {<o:p></o:p></p>
<p class="MsoPlainText">>> - uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;<o:p></o:p></p>
<p class="MsoPlainText">>> + uint64_t addr = min(adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT,<o:p></o:p></p>
<p class="MsoPlainText">>> + AMDGPU_GMC_HOLE_START);<o:p></o:p></p>
<p class="MsoPlainText">>> <o:p></o:p></p>
<p class="MsoPlainText">>> addr -= AMDGPU_VA_RESERVED_SIZE;<o:p></o:p></p>
<p class="MsoPlainText">>> addr = amdgpu_gmc_sign_extend(addr);<o:p></o:p></p>
<p class="MsoPlainText">> _______________________________________________<o:p></o:p></p>
<p class="MsoPlainText">> amd-gfx mailing list<o:p></o:p></p>
<p class="MsoPlainText">> <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">
<span style="text-decoration:none">amd-gfx@lists.freedesktop.org</span></a><o:p></o:p></p>
<p class="MsoPlainText">> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" moz-do-not-send="true">
<span style="text-decoration:none">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</span></a><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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