<div dir="ltr">I've since replaced the LS1012ARDB with a LS1046ARDB, and this works out of the box.<div>The LS1012ARDB does not have an SMMU, which handles hardware coherency on ARM.</div><div>So amdgpu won't work on any ARM without an SMMU.</div><div><br></div><div>Bas Vermeulen</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Jan 10, 2019 at 2:38 PM Koenig, Christian <<a href="mailto:Christian.Koenig@amd.com">Christian.Koenig@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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<div class="gmail-m_7847254306218368447moz-cite-prefix">Am 10.01.19 um 14:31 schrieb Bas Vermeulen:<br>
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<div dir="ltr">On Thu, Jan 10, 2019 at 11:59 AM Christian König <<a href="mailto:ckoenig.leichtzumerken@gmail.com" target="_blank">ckoenig.leichtzumerken@gmail.com</a>> wrote:<br>
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<blockquote type="cite">The PCI Express controller as instantiated on this chip does not support hardware coherency. All incoming PCI Express transactions are made non IO-coherent.
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<div>Would AMDGPU still work with that PCI Express controller, or is this a show-stopper?</div>
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I'm really wondering what this comment in the documentation means.<br>
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As far as I know PCIe doesn't support cache coherency in the downstream and supporting it in the up stream is a must have.<br>
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<div class="gmail-m_7847254306218368447gmail-m_9195313590891012054moz-cite-prefix">So what exactly is meant here with IO-coherent?<br>
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<div>I believe IO Coherent means that when PCIe writes something to CPU memory, the caches are flushed or updated<br>
(or in this case they aren't). I found <a href="https://community.arm.com/processors/b/blog/posts/extended-system-coherency---part-1---cache-coherency-fundamentals" target="_blank">https://community.arm.com/processors/b/blog/posts/extended-system-coherency---part-1---cache-coherency-fundamentals</a> </div>
<div>with this explanation.</div>
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Yeah, but as I said this upstream memory coherency is mandatory for PCIe.<br>
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When a controller doesn't have that it can't call itself a PCIe controller. The spec is pretty clear about that :)<br>
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And to answer the original question: Yes, that would be a totally show-stopper.<br>
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Regards,<br>
Christian.<br>
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<div>Regards,</div>
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<div>Bas Vermeulen</div>
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