<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"><!-- P {margin-top:0;margin-bottom:0;} --></style>
</head>
<body dir="ltr">
<div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr">
<p style="margin-top:0;margin-bottom:0">Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
</p>
</div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Roman.Li@amd.com <Roman.Li@amd.com><br>
<b>Sent:</b> Tuesday, January 29, 2019 3:16:53 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org; Xu, Feifei; Quan, Evan<br>
<b>Cc:</b> Chan, Carl; Wentland, Harry; Li, Roman<br>
<b>Subject:</b> [PATCH] drm/amd/display: Fix fclk idle state</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">From: Roman Li <Roman.Li@amd.com><br>
<br>
[Why]<br>
The earlier change 'Fix 6x4K displays' led to fclk value<br>
idling at higher DPM level.<br>
<br>
[How]<br>
Apply the fix only to respective multi-display configuration.<br>
<br>
Signed-off-by: Roman Li <Roman.Li@amd.com><br>
---<br>
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 10 +++++++++-<br>
1 file changed, 9 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c<br>
index 3c52a4fc921d..bbe051736a18 100644<br>
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c<br>
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c<br>
@@ -627,7 +627,15 @@ static void dce11_pplib_apply_display_requirements(<br>
dc,<br>
context->bw.dce.sclk_khz);<br>
<br>
- pp_display_cfg->min_dcfclock_khz = pp_display_cfg->min_engine_clock_khz;<br>
+ /*<br>
+ * As workaround for >4x4K lightup set dcfclock to min_engine_clock value.<br>
+ * This is not required for less than 5 displays,<br>
+ * thus don't request decfclk in dc to avoid impact<br>
+ * on power saving.<br>
+ *<br>
+ */<br>
+ pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4)?<br>
+ pp_display_cfg->min_engine_clock_khz : 0;<br>
<br>
pp_display_cfg->min_engine_clock_deep_sleep_khz<br>
= context->bw.dce.sclk_deep_sleep_khz;<br>
-- <br>
2.17.1<br>
<br>
_______________________________________________<br>
amd-gfx mailing list<br>
amd-gfx@lists.freedesktop.org<br>
<a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br>
</div>
</span></font></div>
</body>
</html>