<div dir="ltr"><div>Do we actually need the current status? We have the caps of the platform and the device. For the lowest dpm state, we generally want the lowest common gen and then the highest common gen for the highest dpm state. If we use the current status, we will mostly likely end up with the highest gen in the lowest dpm state because generally the highest gen is negotiated at power up.</div><div><br></div><div>Alex<br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Feb 1, 2019 at 5:28 PM Kasiviswanathan, Harish <<a href="mailto:Harish.Kasiviswanathan@amd.com">Harish.Kasiviswanathan@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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<p style="margin-top:0px;margin-bottom:0px">Thanks Alex. I saw that function. It gets caps. The function requires link status (<font size="2"><span style="font-size:11pt">PCI_EXP_LNKSTA</span></font>), the value negotiated.
<br>
</p>
<p style="margin-top:0px;margin-bottom:0px"><br>
</p>
<p style="margin-top:0px;margin-bottom:0px"><font size="2"><span style="font-size:11pt">> I'd rather not access pci config space from the powerplay code because it doesn't work under virtualization.</span></font><br>
</p>
<div>[HK] I will then modify <font size="2"><span style="font-size:11pt">amdgpu_device_get_pcie_info()</span></font> to read "PCI_EXP_LINKSTA" and store that information for future use.</div>
<div><br>
</div>
<div>Best Regards,</div>
<div>Harish</div>
<div><br>
</div>
<div><br>
</div>
<div style="color:rgb(0,0,0)">
<hr style="display:inline-block;width:98%">
<div id="gmail-m_329555177500593286divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Alex Deucher <<a href="mailto:alexdeucher@gmail.com" target="_blank">alexdeucher@gmail.com</a>><br>
<b>Sent:</b> Friday, February 1, 2019 5:09 PM<br>
<b>To:</b> Kasiviswanathan, Harish<br>
<b>Cc:</b> <a href="mailto:amd-gfx@lists.freedesktop.org" target="_blank">amd-gfx@lists.freedesktop.org</a><br>
<b>Subject:</b> Re: [PATCH] drm/amd/powerplay: add override pcie parameters for Vega20 (v2)</font>
<div> </div>
</div>
<div class="gmail-m_329555177500593286BodyFragment"><font size="2"><span style="font-size:11pt">
<div class="gmail-m_329555177500593286PlainText">On Fri, Feb 1, 2019 at 4:17 PM Kasiviswanathan, Harish<br>
<<a href="mailto:Harish.Kasiviswanathan@amd.com" target="_blank">Harish.Kasiviswanathan@amd.com</a>> wrote:<br>
><br>
> v2: Use PCIe link status instead of link capability<br>
> Send override message after SMU enable features<br>
><br>
> Change-Id: Iea2a1ac595cf63a9528ff1e9a6955d14d8c3a6d5<br>
> Signed-off-by: Harish Kasiviswanathan <<a href="mailto:Harish.Kasiviswanathan@amd.com" target="_blank">Harish.Kasiviswanathan@amd.com</a>><br>
> ---<br>
> drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 93 +++++++++++++++-------<br>
> 1 file changed, 64 insertions(+), 29 deletions(-)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
> index da022ca..d166f8c 100644<br>
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
> @@ -771,40 +771,75 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)<br>
> return 0;<br>
> }<br>
><br>
> +/*<br>
> + * Override PCIe link speed and link width for DPM Level 1. PPTable entries<br>
> + * reflect the ASIC capabilities and not the system capabilities. For e.g.<br>
> + * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch<br>
> + * to DPM1, it fails as system doesn't support Gen4.<br>
> + */<br>
> static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)<br>
> {<br>
> struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);<br>
> - uint32_t pcie_speed = 0, pcie_width = 0, pcie_arg;<br>
> + uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;<br>
> int ret;<br>
> + uint16_t lnkstat;<br>
> +<br>
> + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKSTA, &lnkstat);<br>
><br>
> - if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)<br>
> - pcie_speed = 16;<br>
> - else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)<br>
> - pcie_speed = 8;<br>
> - else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)<br>
> - pcie_speed = 5;<br>
> - else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)<br>
> - pcie_speed = 2;<br>
> -<br>
> - if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32)<br>
> - pcie_width = 32;<br>
> - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)<br>
> - pcie_width = 16;<br>
> - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)<br>
> - pcie_width = 12;<br>
> - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)<br>
> - pcie_width = 8;<br>
> - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)<br>
> + switch (lnkstat & PCI_EXP_LNKSTA_CLS) {<br>
> + case PCI_EXP_LNKSTA_CLS_2_5GB:<br>
> + pcie_gen = 0;<br>
> + break;<br>
> + case PCI_EXP_LNKSTA_CLS_5_0GB:<br>
> + pcie_gen = 1;<br>
> + break;<br>
> + case PCI_EXP_LNKSTA_CLS_8_0GB:<br>
> + pcie_gen = 2;<br>
> + break;<br>
> + case PCI_EXP_LNKSTA_CLS_16_0GB:<br>
> + pcie_gen = 3;<br>
> + break;<br>
> + default:<br>
> + pr_warn("Unknown PCI link speed %x\n",<br>
> + lnkstat & PCI_EXP_LNKSTA_CLS);<br>
> + }<br>
> +<br>
> +<br>
> + switch ((lnkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT) {<br>
> + case 32:<br>
> + pcie_width = 7;<br>
> + break;<br>
> + case 16:<br>
> + pcie_width = 6;<br>
> + break;<br>
> + case 12:<br>
> + pcie_width = 5;<br>
> + break;<br>
> + case 8:<br>
> pcie_width = 4;<br>
> - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)<br>
> + break;<br>
> + case 4:<br>
> + pcie_width = 3;<br>
> + break;<br>
> + case 2:<br>
> pcie_width = 2;<br>
> - else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)<br>
> + break;<br>
> + case 1:<br>
> pcie_width = 1;<br>
> + break;<br>
> + default:<br>
> + pr_warn("Unknown PCI link width %x\n",<br>
> + lnkstat & PCI_EXP_LNKSTA_CLS);<br>
> + }<br>
><br>
<br>
We already get the link caps for both the device and the platform in<br>
amdgpu_device_get_pcie_info(). Is that info not adequate? I'd rather<br>
not access pci config space from the powerplay code because it doesn't<br>
work under virtualization.<br>
<br>
Alex<br>
<br>
> - pcie_arg = pcie_width | (pcie_speed << 8);<br>
> -<br>
> + /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1<br>
> + * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4<br>
> + * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32<br>
> + */<br>
> + smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;<br>
> ret = smum_send_msg_to_smc_with_parameter(hwmgr,<br>
> - PPSMC_MSG_OverridePcieParameters, pcie_arg);<br>
> + PPSMC_MSG_OverridePcieParameters, smu_pcie_arg);<br>
> +<br>
> PP_ASSERT_WITH_CODE(!ret,<br>
> "[OverridePcieParameters] Attempt to override pcie params failed!",<br>
> return ret);<br>
> @@ -1611,11 +1646,6 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)<br>
> "[EnableDPMTasks] Failed to initialize SMC table!",<br>
> return result);<br>
><br>
> - result = vega20_override_pcie_parameters(hwmgr);<br>
> - PP_ASSERT_WITH_CODE(!result,<br>
> - "[EnableDPMTasks] Failed to override pcie parameters!",<br>
> - return result);<br>
> -<br>
> result = vega20_run_btc(hwmgr);<br>
> PP_ASSERT_WITH_CODE(!result,<br>
> "[EnableDPMTasks] Failed to run btc!",<br>
> @@ -1631,6 +1661,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)<br>
> "[EnableDPMTasks] Failed to enable all smu features!",<br>
> return result);<br>
><br>
> + result = vega20_override_pcie_parameters(hwmgr);<br>
> + PP_ASSERT_WITH_CODE(!result,<br>
> + "[EnableDPMTasks] Failed to override pcie parameters!",<br>
> + return result);<br>
> +<br>
> result = vega20_notify_smc_display_change(hwmgr);<br>
> PP_ASSERT_WITH_CODE(!result,<br>
> "[EnableDPMTasks] Failed to notify smc display change!",<br>
> --<br>
> 2.7.4<br>
><br>
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