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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tom St Denis <tstdenis82@gmail.com><br>
<b>Sent:</b> Tuesday, March 5, 2019 10:17 AM<br>
<b>To:</b> amd-gfx mailing list<br>
<b>Subject:</b> Re: [PATCH] drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers</font>
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<div dir="ltr">Hi,
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<div>Alex can I get an RB on this :-)</div>
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<div>Thanks,</div>
<div>Tom</div>
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<div dir="ltr" class="x_gmail_attr">On Mon, Mar 4, 2019 at 10:59 AM StDenis, Tom <<a href="mailto:Tom.StDenis@amd.com">Tom.StDenis@amd.com</a>> wrote:<br>
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<blockquote class="x_gmail_quote" style="margin:0px 0px 0px 0.8ex; border-left:1px solid rgb(204,204,204); padding-left:1ex">
Signed-off-by: Tom St Denis <<a href="mailto:tom.stdenis@amd.com" target="_blank">tom.stdenis@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 2 ++<br>
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 5 +++++<br>
2 files changed, 7 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h<br>
index 442ca7c471a5..6109f5ad25ad 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h<br>
@@ -141,6 +141,8 @@<br>
#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1<br>
#define mmUVD_GPCOM_VCPU_DATA1 0x03c5<br>
#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1<br>
+#define mmUVD_ENGINE_CNTL 0x03c6<br>
+#define mmUVD_ENGINE_CNTL_BASE_IDX 1<br>
#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG 0x03d2<br>
#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX 1<br>
#define mmUVD_UDEC_ADDR_CONFIG 0x03d3<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h<br>
index 63457f9df4c5..f84bed6eecb9 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h<br>
@@ -312,6 +312,11 @@<br>
//UVD_GPCOM_VCPU_DATA1<br>
#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0<br>
#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL<br>
+//UVD_ENGINE_CNTL<br>
+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1<br>
+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0<br>
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2<br>
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1<br>
//UVD_UDEC_DBW_UV_ADDR_CONFIG<br>
#define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0<br>
#define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3<br>
-- <br>
2.17.2<br>
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