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<p class="MsoPlainText">Copied register definitions below. I guess with this change, you changed how the IH block treat new interrupt when ring is full. Before this change, IH keep new interrupt in the ring and overwrite oldest interrupt. After your change,
IH will simply drop new interrupt and keep old interrupt in the ring (keep wptr unchanged).
<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Is above understanding correct? If yes, can you explain why the new scheme is more reliable? If this is more reliable, should we use this scheme for all 3 interrupt ring?<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Geneva;color:black">RB_FULL_DRAIN_ENABLE<o:p></o:p></span></p>
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<p class="MsoNormal" align="center" style="text-align:center"><span style="font-size:9.0pt;font-family:Geneva;color:black">9<o:p></o:p></span></p>
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<p class="MsoNormal" align="center" style="text-align:center"><span style="font-size:9.0pt;font-family:Geneva;color:black">0x0<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Geneva;color:#0000AA">When Ring Buffer is full, this enables draining of interrupts to prevent back pressure to IH clients.<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:9.0pt;font-family:Geneva;color:#0000AA"> <u>POSSIBLE VALUES:</u><br>
00 - Disable <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Geneva;color:black">WPTR_OVERFLOW_ENABLE<o:p></o:p></span></p>
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<p class="MsoNormal" align="center" style="text-align:center"><span style="font-size:9.0pt;font-family:Geneva;color:black">16<o:p></o:p></span></p>
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<p class="MsoNormal" align="center" style="text-align:center"><span style="font-size:9.0pt;font-family:Geneva;color:black">0x1<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Geneva;color:#0000AA">Ring Buffer write pointer overflow.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:9.0pt;font-family:Geneva;color:#0000AA"> POSSIBLE VALUES:<br>
00 - Disable <br>
01 - Enable <o:p></o:p></span></p>
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<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Regards,<o:p></o:p></p>
<p class="MsoPlainText">Oak<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">-----Original Message-----<br>
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Christian König<br>
Sent: Wednesday, March 6, 2019 4:29 AM<br>
To: amd-gfx@lists.freedesktop.org<br>
Subject: Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config</p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Ping? Can anybody review this?<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Thanks,<o:p></o:p></p>
<p class="MsoPlainText">Christian.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Am 04.03.19 um 20:10 schrieb Christian König:<o:p></o:p></p>
<p class="MsoPlainText">> Disable overflow and enable full drain. This makes fault handling on
<o:p></o:p></p>
<p class="MsoPlainText">> ring 1 much more reliable since we don't generate back pressure any more.<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> Signed-off-by: Christian König <<a href="mailto:christian.koenig@amd.com"><span style="color:windowtext;text-decoration:none">christian.koenig@amd.com</span></a>><o:p></o:p></p>
<p class="MsoPlainText">> ---<o:p></o:p></p>
<p class="MsoPlainText">> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++++<o:p></o:p></p>
<p class="MsoPlainText">> 1 file changed, 4 insertions(+)<o:p></o:p></p>
<p class="MsoPlainText">><o:p> </o:p></p>
<p class="MsoPlainText">> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c <o:p>
</o:p></p>
<p class="MsoPlainText">> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<o:p></o:p></p>
<p class="MsoPlainText">> index 6d1f804277f8..d4a3cc413af8 100644<o:p></o:p></p>
<p class="MsoPlainText">> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<o:p></o:p></p>
<p class="MsoPlainText">> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<o:p></o:p></p>
<p class="MsoPlainText">> @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct
<o:p></o:p></p>
<p class="MsoPlainText">> amdgpu_device *adev)<o:p></o:p></p>
<p class="MsoPlainText">> <o:p></o:p></p>
<p class="MsoPlainText">> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);<o:p></o:p></p>
<p class="MsoPlainText">> ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);<o:p></o:p></p>
<p class="MsoPlainText">> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,<o:p></o:p></p>
<p class="MsoPlainText">> + WPTR_OVERFLOW_ENABLE, 0);<o:p></o:p></p>
<p class="MsoPlainText">> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,<o:p></o:p></p>
<p class="MsoPlainText">> + RB_FULL_DRAIN_ENABLE, 1);<o:p></o:p></p>
<p class="MsoPlainText">> WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);<o:p></o:p></p>
<p class="MsoPlainText">> <o:p></o:p></p>
<p class="MsoPlainText">> /* set rptr, wptr to 0 */<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">_______________________________________________<o:p></o:p></p>
<p class="MsoPlainText">amd-gfx mailing list<o:p></o:p></p>
<p class="MsoPlainText"><a href="mailto:amd-gfx@lists.freedesktop.org"><span style="color:windowtext;text-decoration:none">amd-gfx@lists.freedesktop.org</span></a><o:p></o:p></p>
<p class="MsoPlainText"><a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx"><span style="color:windowtext;text-decoration:none">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</span></a><o:p></o:p></p>
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