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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Tuesday, March 26, 2019 6:13 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Quan, Evan<br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: fix possible hang with 3+ 4K monitors</font>
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<div class="PlainText">If DAL requires to force MCLK high, the FCLK will be<br>
forced to high also.<br>
<br>
Change-Id: Iaff8956ca1faafaf904f0bec108f566e8bbf6a64<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 10 +++++++++-<br>
1 file changed, 9 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
index 3f349ada8de0..38dbec3caa01 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
@@ -3471,6 +3471,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)<br>
struct vega20_single_dpm_table *dpm_table;<br>
bool vblank_too_short = false;<br>
bool disable_mclk_switching;<br>
+ bool disable_fclk_switching;<br>
uint32_t i, latency;<br>
<br>
disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&<br>
@@ -3546,13 +3547,20 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)<br>
if (hwmgr->display_config->nb_pstate_switch_disable)<br>
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;<br>
<br>
+ if ((disable_mclk_switching &&<br>
+ (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||<br>
+ hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)<br>
+ disable_fclk_switching = true;<br>
+ else<br>
+ disable_fclk_switching = false;<br>
+<br>
/* fclk */<br>
dpm_table = &(data->dpm_table.fclk_table);<br>
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;<br>
dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;<br>
dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;<br>
dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;<br>
- if (hwmgr->display_config->nb_pstate_switch_disable)<br>
+ if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)<br>
dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;<br>
<br>
/* vclk */<br>
-- <br>
2.21.0<br>
<br>
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