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Series is:</div>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Tuesday, April 23, 2019 4:37 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Deucher, Alexander; Quan, Evan<br>
<b>Subject:</b> [PATCH 5/5] drm/amd/powerplay: support hwmon temperature channel labels V2</font>
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<div class="PlainText">Expose temp[1-3]_label hwmon interfaces. While temp2_label<br>
and temp3_label are visible for SOC15 dGPUs only.<br>
<br>
- V2: correct temp1_label as "edge"<br>
<br>
Change-Id: I7f1e10c52ec21d272027554cdf6da97103e0be58<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        | 35 ++++++++++++++++++-<br>
 .../gpu/drm/amd/include/kgd_pp_interface.h    |  7 ++++<br>
 2 files changed, 41 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
index 291c06f40dba..4fe1b58892a2 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
@@ -120,6 +120,15 @@ static const struct cg_flag_name clocks[] = {<br>
         {0, NULL},<br>
 };<br>
 <br>
+static const struct hwmon_temp_label {<br>
+       enum PP_HWMON_TEMP channel;<br>
+       const char *label;<br>
+} temp_label[] = {<br>
+       {PP_TEMP_EDGE, "edge"},<br>
+       {PP_TEMP_JUNCTION, "junction"},<br>
+       {PP_TEMP_MEM, "mem"},<br>
+};<br>
+<br>
 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)<br>
 {<br>
         if (adev->pm.dpm_enabled) {<br>
@@ -1511,6 +1520,19 @@ static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,<br>
         return snprintf(buf, PAGE_SIZE, "%d\n", temp);<br>
 }<br>
 <br>
+static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,<br>
+                                            struct device_attribute *attr,<br>
+                                            char *buf)<br>
+{<br>
+       struct amdgpu_device *adev = dev_get_drvdata(dev);<br>
+       int channel = to_sensor_dev_attr(attr)->index;<br>
+<br>
+       if (channel >= PP_TEMP_MAX)<br>
+               return -EINVAL;<br>
+<br>
+       return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);<br>
+}<br>
+<br>
 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,<br>
                                              struct device_attribute *attr,<br>
                                              char *buf)<br>
@@ -2109,6 +2131,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,<br>
  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius<br>
  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only<br>
  *<br>
+ * - temp[1-3]_label: temperature channel label<br>
+ *   - temp2_label and temp3_label are supported on SOC15 dGPUs only<br>
+ *<br>
  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius<br>
  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only<br>
  *<br>
@@ -2176,6 +2201,9 @@ static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP<br>
 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);<br>
 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);<br>
 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);<br>
+static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);<br>
+static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);<br>
+static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);<br>
 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);<br>
 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);<br>
 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);<br>
@@ -2211,6 +2239,9 @@ static struct attribute *hwmon_attributes[] = {<br>
         &sensor_dev_attr_temp1_emergency.dev_attr.attr,<br>
         &sensor_dev_attr_temp2_emergency.dev_attr.attr,<br>
         &sensor_dev_attr_temp3_emergency.dev_attr.attr,<br>
+       &sensor_dev_attr_temp1_label.dev_attr.attr,<br>
+       &sensor_dev_attr_temp2_label.dev_attr.attr,<br>
+       &sensor_dev_attr_temp3_label.dev_attr.attr,<br>
         &sensor_dev_attr_pwm1.dev_attr.attr,<br>
         &sensor_dev_attr_pwm1_enable.dev_attr.attr,<br>
         &sensor_dev_attr_pwm1_min.dev_attr.attr,<br>
@@ -2344,7 +2375,9 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,<br>
              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||<br>
              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||<br>
              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||<br>
-            attr == &sensor_dev_attr_temp3_input.dev_attr.attr))<br>
+            attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||<br>
+            attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||<br>
+            attr == &sensor_dev_attr_temp3_label.dev_attr.attr))<br>
                 return 0;<br>
 <br>
         return effective_mode;<br>
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h<br>
index a8bf8e90ceeb..30788d510576 100644<br>
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h<br>
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h<br>
@@ -162,6 +162,13 @@ struct pp_states_info {<br>
         uint32_t states[16];<br>
 };<br>
 <br>
+enum PP_HWMON_TEMP {<br>
+       PP_TEMP_EDGE = 0,<br>
+       PP_TEMP_JUNCTION,<br>
+       PP_TEMP_MEM,<br>
+       PP_TEMP_MAX<br>
+};<br>
+<br>
 #define PP_GROUP_MASK        0xF0000000<br>
 #define PP_GROUP_SHIFT       28<br>
 <br>
-- <br>
2.21.0<br>
<br>
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