<div dir="ltr"><div>Reviewed-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>></div><div><br></div><div>Marek<br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, May 10, 2019 at 1:58 PM Christian König <<a href="mailto:ckoenig.leichtzumerken@gmail.com">ckoenig.leichtzumerken@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">As far as we know this was never used by userspace and so should be removed.<br>
<br>
Signed-off-by: Christian König <<a href="mailto:christian.koenig@amd.com" target="_blank">christian.koenig@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 6 ++--<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 21 ++---------<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 +++---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 24 ++-----------<br>
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 32 +++--------------<br>
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 32 +++--------------<br>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 ++++-----------------<br>
7 files changed, 28 insertions(+), 137 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c<br>
index 5c79da8e1150..d497467b7fc6 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c<br>
@@ -81,9 +81,9 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,<br>
return -ENOMEM;<br>
<br>
kref_init(&list->refcount);<br>
- list->gds_obj = adev->gds.gds_gfx_bo;<br>
- list->gws_obj = adev->gds.gws_gfx_bo;<br>
- list->oa_obj = adev->gds.oa_gfx_bo;<br>
+ list->gds_obj = NULL;<br>
+ list->gws_obj = NULL;<br>
+ list->oa_obj = NULL;<br>
<br>
array = amdgpu_bo_list_array_entry(list, 0);<br>
memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h<br>
index f89f5734d985..dad2186f4ed5 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h<br>
@@ -27,26 +27,11 @@<br>
struct amdgpu_ring;<br>
struct amdgpu_bo;<br>
<br>
-struct amdgpu_gds_asic_info {<br>
- uint32_t total_size;<br>
- uint32_t gfx_partition_size;<br>
- uint32_t cs_partition_size;<br>
-};<br>
-<br>
struct amdgpu_gds {<br>
- struct amdgpu_gds_asic_info mem;<br>
- struct amdgpu_gds_asic_info gws;<br>
- struct amdgpu_gds_asic_info oa;<br>
+ uint32_t gds_size;<br>
+ uint32_t gws_size;<br>
+ uint32_t oa_size;<br>
uint32_t gds_compute_max_wave_id;<br>
-<br>
- /* At present, GDS, GWS and OA resources for gfx (graphics)<br>
- * is always pre-allocated and available for graphics operation.<br>
- * Such resource is shared between all gfx clients.<br>
- * TODO: move this operation to user space<br>
- * */<br>
- struct amdgpu_bo* gds_gfx_bo;<br>
- struct amdgpu_bo* gws_gfx_bo;<br>
- struct amdgpu_bo* oa_gfx_bo;<br>
};<br>
<br>
struct amdgpu_gds_reg_offset {<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
index da7b4fe8ade3..87a93874d71e 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
@@ -590,13 +590,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file<br>
struct drm_amdgpu_info_gds gds_info;<br>
<br>
memset(&gds_info, 0, sizeof(gds_info));<br>
- gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size;<br>
- gds_info.compute_partition_size = adev->gds.mem.cs_partition_size;<br>
- gds_info.gds_total_size = adev->gds.mem.total_size;<br>
- gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size;<br>
- gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size;<br>
- gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size;<br>
- gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size;<br>
+ gds_info.compute_partition_size = adev->gds.gds_size;<br>
+ gds_info.gds_total_size = adev->gds.gds_size;<br>
+ gds_info.gws_per_compute_partition = adev->gds.gws_size;<br>
+ gds_info.oa_per_compute_partition = adev->gds.oa_size;<br>
return copy_to_user(out, &gds_info,<br>
min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;<br>
}<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br>
index c14198737dcd..b25922e3d1ed 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br>
@@ -1758,44 +1758,26 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)<br>
<br>
/* Initialize various on-chip memory pools */<br>
r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,<br>
- adev->gds.mem.total_size);<br>
+ adev->gds.gds_size);<br>
if (r) {<br>
DRM_ERROR("Failed initializing GDS heap.\n");<br>
return r;<br>
}<br>
<br>
- r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,<br>
- 4, AMDGPU_GEM_DOMAIN_GDS,<br>
- &adev->gds.gds_gfx_bo, NULL, NULL);<br>
- if (r)<br>
- return r;<br>
-<br>
r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,<br>
- adev->gds.gws.total_size);<br>
+ adev->gds.gws_size);<br>
if (r) {<br>
DRM_ERROR("Failed initializing gws heap.\n");<br>
return r;<br>
}<br>
<br>
- r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,<br>
- 1, AMDGPU_GEM_DOMAIN_GWS,<br>
- &adev->gds.gws_gfx_bo, NULL, NULL);<br>
- if (r)<br>
- return r;<br>
-<br>
r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,<br>
- adev->gds.oa.total_size);<br>
+ adev->gds.oa_size);<br>
if (r) {<br>
DRM_ERROR("Failed initializing oa heap.\n");<br>
return r;<br>
}<br>
<br>
- r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,<br>
- 1, AMDGPU_GEM_DOMAIN_OA,<br>
- &adev->gds.oa_gfx_bo, NULL, NULL);<br>
- if (r)<br>
- return r;<br>
-<br>
/* Register debugfs entries for amdgpu_ttm */<br>
r = amdgpu_ttm_debugfs_init(adev);<br>
if (r) {<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br>
index a59e0fdf5a97..4cd1731d62fd 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br>
@@ -4493,12 +4493,8 @@ static int gfx_v7_0_sw_init(void *handle)<br>
<br>
static int gfx_v7_0_sw_fini(void *handle)<br>
{<br>
- int i;<br>
struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
-<br>
- amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);<br>
- amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);<br>
- amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);<br>
+ int i;<br>
<br>
for (i = 0; i < adev->gfx.num_gfx_rings; i++)<br>
amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);<br>
@@ -5070,30 +5066,10 @@ static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)<br>
static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)<br>
{<br>
/* init asci gds info */<br>
- adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);<br>
- adev->gds.gws.total_size = 64;<br>
- adev->gds.oa.total_size = 16;<br>
+ adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);<br>
+ adev->gds.gws_size = 64;<br>
+ adev->gds.oa_size = 16;<br>
adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);<br>
-<br>
- if (adev->gds.mem.total_size == 64 * 1024) {<br>
- adev->gds.mem.gfx_partition_size = 4096;<br>
- adev->gds.mem.cs_partition_size = 4096;<br>
-<br>
- adev->gds.gws.gfx_partition_size = 4;<br>
- adev->gds.gws.cs_partition_size = 4;<br>
-<br>
- adev->gds.oa.gfx_partition_size = 4;<br>
- adev->gds.oa.cs_partition_size = 1;<br>
- } else {<br>
- adev->gds.mem.gfx_partition_size = 1024;<br>
- adev->gds.mem.cs_partition_size = 1024;<br>
-<br>
- adev->gds.gws.gfx_partition_size = 16;<br>
- adev->gds.gws.cs_partition_size = 16;<br>
-<br>
- adev->gds.oa.gfx_partition_size = 4;<br>
- adev->gds.oa.cs_partition_size = 4;<br>
- }<br>
}<br>
<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
index 02955e6e9dd9..25400b708722 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
@@ -2057,12 +2057,8 @@ static int gfx_v8_0_sw_init(void *handle)<br>
<br>
static int gfx_v8_0_sw_fini(void *handle)<br>
{<br>
- int i;<br>
struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
-<br>
- amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);<br>
- amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);<br>
- amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);<br>
+ int i;<br>
<br>
for (i = 0; i < adev->gfx.num_gfx_rings; i++)<br>
amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);<br>
@@ -7010,30 +7006,10 @@ static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)<br>
static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)<br>
{<br>
/* init asci gds info */<br>
- adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);<br>
- adev->gds.gws.total_size = 64;<br>
- adev->gds.oa.total_size = 16;<br>
+ adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);<br>
+ adev->gds.gws_size = 64;<br>
+ adev->gds.oa_size = 16;<br>
adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);<br>
-<br>
- if (adev->gds.mem.total_size == 64 * 1024) {<br>
- adev->gds.mem.gfx_partition_size = 4096;<br>
- adev->gds.mem.cs_partition_size = 4096;<br>
-<br>
- adev->gds.gws.gfx_partition_size = 4;<br>
- adev->gds.gws.cs_partition_size = 4;<br>
-<br>
- adev->gds.oa.gfx_partition_size = 4;<br>
- adev->gds.oa.cs_partition_size = 1;<br>
- } else {<br>
- adev->gds.mem.gfx_partition_size = 1024;<br>
- adev->gds.mem.cs_partition_size = 1024;<br>
-<br>
- adev->gds.gws.gfx_partition_size = 16;<br>
- adev->gds.gws.cs_partition_size = 16;<br>
-<br>
- adev->gds.oa.gfx_partition_size = 4;<br>
- adev->gds.oa.cs_partition_size = 4;<br>
- }<br>
}<br>
<br>
static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
index fc6d8c1fd32b..fac38429685d 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
@@ -1461,8 +1461,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)<br>
<br>
/* GDS reserve memory: 64 bytes alignment */<br>
adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);<br>
- adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;<br>
- adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;<br>
+ adev->gds.gds_size -= adev->gfx.ngg.gds_reserve_size;<br>
adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);<br>
adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);<br>
<br>
@@ -1570,7 +1569,7 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)<br>
<br>
gfx_v9_0_write_data_to_reg(ring, 0, false,<br>
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),<br>
- (adev->gds.mem.total_size +<br>
+ (adev->gds.gds_size +<br>
adev->gfx.ngg.gds_reserve_size));<br>
<br>
amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));<br>
@@ -1784,10 +1783,6 @@ static int gfx_v9_0_sw_fini(void *handle)<br>
kfree(ras_if);<br>
}<br>
<br>
- amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);<br>
- amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);<br>
- amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);<br>
-<br>
for (i = 0; i < adev->gfx.num_gfx_rings; i++)<br>
amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);<br>
for (i = 0; i < adev->gfx.num_compute_rings; i++)<br>
@@ -5309,13 +5304,13 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)<br>
case CHIP_VEGA10:<br>
case CHIP_VEGA12:<br>
case CHIP_VEGA20:<br>
- adev->gds.mem.total_size = 0x10000;<br>
+ adev->gds.gds_size = 0x10000;<br>
break;<br>
case CHIP_RAVEN:<br>
- adev->gds.mem.total_size = 0x1000;<br>
+ adev->gds.gds_size = 0x1000;<br>
break;<br>
default:<br>
- adev->gds.mem.total_size = 0x10000;<br>
+ adev->gds.gds_size = 0x10000;<br>
break;<br>
}<br>
<br>
@@ -5339,28 +5334,8 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)<br>
break;<br>
}<br>
<br>
- adev->gds.gws.total_size = 64;<br>
- adev->gds.oa.total_size = 16;<br>
-<br>
- if (adev->gds.mem.total_size == 64 * 1024) {<br>
- adev->gds.mem.gfx_partition_size = 4096;<br>
- adev->gds.mem.cs_partition_size = 4096;<br>
-<br>
- adev->gds.gws.gfx_partition_size = 4;<br>
- adev->gds.gws.cs_partition_size = 4;<br>
-<br>
- adev->gds.oa.gfx_partition_size = 4;<br>
- adev->gds.oa.cs_partition_size = 1;<br>
- } else {<br>
- adev->gds.mem.gfx_partition_size = 1024;<br>
- adev->gds.mem.cs_partition_size = 1024;<br>
-<br>
- adev->gds.gws.gfx_partition_size = 16;<br>
- adev->gds.gws.cs_partition_size = 16;<br>
-<br>
- adev->gds.oa.gfx_partition_size = 4;<br>
- adev->gds.oa.cs_partition_size = 4;<br>
- }<br>
+ adev->gds.gws_size = 64;<br>
+ adev->gds.oa_size = 16;<br>
}<br>
<br>
static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,<br>
-- <br>
2.17.1<br>
<br>
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