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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tiecheng Zhou <Tiecheng.Zhou@amd.com><br>
<b>Sent:</b> Monday, May 13, 2019 11:34 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhou, Tiecheng; Deng, Emily<br>
<b>Subject:</b> [PATCH] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE</font>
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<div class="PlainText">[CAUTION: External Email]<br>
<br>
it requires to initialize HDP_NONSURFACE_BASE, so as to avoid<br>
using the value left by a previous VM under sriov scenario.<br>
<br>
Signed-off-by: Emily Deng <Emily.Deng@amd.com><br>
Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +++++<br>
1 file changed, 5 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
index be729e7..e96684e 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
@@ -1181,6 +1181,11 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)<br>
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);<br>
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);<br>
<br>
+ if (amdgpu_sriov_vf(adev)) {<br>
+ WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));<br>
+ WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));<br>
+ }<br>
+<br>
/* After HDP is initialized, flush HDP.*/<br>
adev->nbio_funcs->hdp_flush(adev, NULL);<br>
<br>
--<br>
2.7.4<br>
<br>
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