<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=gb2312"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> Hi Alex Many thanks for your review. I will merge these two patches into one and submit again. Best Regards Yintian Tao </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">发件人: Alex Deucher <alexdeucher@gmail.com> 发送时间: 2019年5月17日 22:34:30 收件人: Tao, Yintian 抄送: amd-gfx@lists.freedesktop.org; Koenig, Christian; Deucher, Alexander; Huang, Trigger 主题: Re: [PATCH] drm/amdgpu: set correct vram_width for vega10 under sriov <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">[CAUTION: External Email] How about combining these two patches into one? This seems cleaner. Alex On Thu, May 16, 2019 at 10:39 PM Tao, Yintian <Yintian.Tao@amd.com> wrote: > > Ping... > > Hi Christian and Alex > > > Can you help review this? Thanks in advance. > > > Best Regards > Yintian Tao > > -----Original Message----- > From: Yintian Tao <yttao@amd.com> > Sent: Thursday, May 16, 2019 8:03 PM > To: amd-gfx@lists.freedesktop.org > Cc: Tao, Yintian <Yintian.Tao@amd.com>; Huang, Trigger <Trigger.Huang@amd.com> > Subject: [PATCH] drm/amdgpu: set correct vram_width for vega10 under sriov > > For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, and DF related registers is not readable, seems hardcord is the only way to set the correct vram_width > > Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> > Signed-off-by: Yintian Tao <yttao@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index c221570..a417763 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -848,6 +848,13 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) > adev->gmc.vram_width = numchan * chansize; > } > > + /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, > + * and DF related registers is not readable, seems hardcord is the > + * only way to set the correct vram_width */ > + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { > + adev->gmc.vram_width = 2048; > + } > + > /* size in MB on si */ > adev->gmc.mc_vram_size = > adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a> </div> </div> </body> </html>