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Did you see the patch I attached?</div>
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Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Tao, Yintian<br>
<b>Sent:</b> Friday, May 17, 2019 10:51 AM<br>
<b>To:</b> Alex Deucher<br>
<b>Cc:</b> amd-gfx@lists.freedesktop.org; Koenig, Christian; Deucher, Alexander; Huang, Trigger<br>
<b>Subject:</b> 答复: [PATCH] drm/amdgpu: set correct vram_width for vega10 under sriov</font>
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<p style="margin-top:0; margin-bottom:0">Hi Alex</p>
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<p style="margin-top:0; margin-bottom:0">Many thanks for your review. I will merge these two patches into one and submit again.</p>
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<p style="margin-top:0; margin-bottom:0">Best Regards</p>
<p style="margin-top:0; margin-bottom:0">Yintian Tao</p>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>发件人:</b> Alex Deucher <alexdeucher@gmail.com><br>
<b>发送时间:</b> 2019年5月17日 22:34:30<br>
<b>收件人:</b> Tao, Yintian<br>
<b>抄送:</b> amd-gfx@lists.freedesktop.org; Koenig, Christian; Deucher, Alexander; Huang, Trigger<br>
<b>主题:</b> Re: [PATCH] drm/amdgpu: set correct vram_width for vega10 under sriov</font>
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<div class="x_PlainText">[CAUTION: External Email]<br>
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How about combining these two patches into one? This seems cleaner.<br>
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Alex<br>
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On Thu, May 16, 2019 at 10:39 PM Tao, Yintian <Yintian.Tao@amd.com> wrote:<br>
><br>
> Ping...<br>
><br>
> Hi Christian and Alex<br>
><br>
><br>
> Can you help review this? Thanks in advance.<br>
><br>
><br>
> Best Regards<br>
> Yintian Tao<br>
><br>
> -----Original Message-----<br>
> From: Yintian Tao <yttao@amd.com><br>
> Sent: Thursday, May 16, 2019 8:03 PM<br>
> To: amd-gfx@lists.freedesktop.org<br>
> Cc: Tao, Yintian <Yintian.Tao@amd.com>; Huang, Trigger <Trigger.Huang@amd.com><br>
> Subject: [PATCH] drm/amdgpu: set correct vram_width for vega10 under sriov<br>
><br>
> For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, and DF related registers is not readable, seems hardcord is the only way to set the correct vram_width<br>
><br>
> Signed-off-by: Trigger Huang <Trigger.Huang@amd.com><br>
> Signed-off-by: Yintian Tao <yttao@amd.com><br>
> ---<br>
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++++++<br>
> 1 file changed, 7 insertions(+)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
> index c221570..a417763 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
> @@ -848,6 +848,13 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)<br>
> adev->gmc.vram_width = numchan * chansize;<br>
> }<br>
><br>
> + /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,<br>
> + * and DF related registers is not readable, seems hardcord is the<br>
> + * only way to set the correct vram_width */<br>
> + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {<br>
> + adev->gmc.vram_width = 2048;<br>
> + }<br>
> +<br>
> /* size in MB on si */<br>
> adev->gmc.mc_vram_size =<br>
> adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;<br>
> --<br>
> 2.7.4<br>
><br>
> _______________________________________________<br>
> amd-gfx mailing list<br>
> amd-gfx@lists.freedesktop.org<br>
> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br>
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