<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style>
</head>
<body dir="ltr">
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
</div>
<div id="appendonsend"></div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Tuesday, June 25, 2019 4:49 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Quan, Evan<br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: support runtime ppfeatures setting on Navi10</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Implement Navi10 backend for runtime ppfeatures status retrieving<br>
and setting support.<br>
<br>
Change-Id: Ib498b934c260e351c6cafedcd865fd931319e7a3<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 165 +++++++++++++++++++++<br>
1 file changed, 165 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
index ac4b3fc97a8d..3d61372db551 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
@@ -1275,6 +1275,169 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_<br>
return 0;<br>
}<br>
<br>
+static int navi10_get_ppfeature_status(struct smu_context *smu,<br>
+ char *buf)<br>
+{<br>
+ static const char *ppfeature_name[] = {<br>
+ "DPM_PREFETCHER",<br>
+ "DPM_GFXCLK",<br>
+ "DPM_GFX_PACE",<br>
+ "DPM_UCLK",<br>
+ "DPM_SOCCLK",<br>
+ "DPM_MP0CLK",<br>
+ "DPM_LINK",<br>
+ "DPM_DCEFCLK",<br>
+ "MEM_VDDCI_SCALING",<br>
+ "MEM_MVDD_SCALING",<br>
+ "DS_GFXCLK",<br>
+ "DS_SOCCLK",<br>
+ "DS_LCLK",<br>
+ "DS_DCEFCLK",<br>
+ "DS_UCLK",<br>
+ "GFX_ULV",<br>
+ "FW_DSTATE",<br>
+ "GFXOFF",<br>
+ "BACO",<br>
+ "VCN_PG",<br>
+ "JPEG_PG",<br>
+ "USB_PG",<br>
+ "RSMU_SMN_CG",<br>
+ "PPT",<br>
+ "TDC",<br>
+ "GFX_EDC",<br>
+ "APCC_PLUS",<br>
+ "GTHR",<br>
+ "ACDC",<br>
+ "VR0HOT",<br>
+ "VR1HOT",<br>
+ "FW_CTF",<br>
+ "FAN_CONTROL",<br>
+ "THERMAL",<br>
+ "GFX_DCS",<br>
+ "RM",<br>
+ "LED_DISPLAY",<br>
+ "GFX_SS",<br>
+ "OUT_OF_BAND_MONITOR",<br>
+ "TEMP_DEPENDENT_VMIN",<br>
+ "MMHUB_PG",<br>
+ "ATHUB_PG"};<br>
+ static const char *output_title[] = {<br>
+ "FEATURES",<br>
+ "BITMASK",<br>
+ "ENABLEMENT"};<br>
+ uint64_t features_enabled;<br>
+ uint32_t feature_mask[2];<br>
+ int i;<br>
+ int ret = 0;<br>
+ int size = 0;<br>
+<br>
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
+ PP_ASSERT_WITH_CODE(!ret,<br>
+ "[GetPPfeatureStatus] Failed to get enabled smc features!",<br>
+ return ret);<br>
+ features_enabled = (uint64_t)feature_mask[0] |<br>
+ (uint64_t)feature_mask[1] << 32;<br>
+<br>
+ size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);<br>
+ size += sprintf(buf + size, "%-19s %-22s %s\n",<br>
+ output_title[0],<br>
+ output_title[1],<br>
+ output_title[2]);<br>
+ for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {<br>
+ size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",<br>
+ ppfeature_name[i],<br>
+ 1ULL << i,<br>
+ (features_enabled & (1ULL << i)) ? "Y" : "N");<br>
+ }<br>
+<br>
+ return size;<br>
+}<br>
+<br>
+static int navi10_enable_smc_features(struct smu_context *smu,<br>
+ bool enabled,<br>
+ uint64_t feature_masks)<br>
+{<br>
+ struct smu_feature *feature = &smu->smu_feature;<br>
+ uint32_t feature_low, feature_high;<br>
+ uint32_t feature_mask[2];<br>
+ int ret = 0;<br>
+<br>
+ feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);<br>
+ feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);<br>
+<br>
+ if (enabled) {<br>
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,<br>
+ feature_low);<br>
+ if (ret)<br>
+ return ret;<br>
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,<br>
+ feature_high);<br>
+ if (ret)<br>
+ return ret;<br>
+ } else {<br>
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,<br>
+ feature_low);<br>
+ if (ret)<br>
+ return ret;<br>
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,<br>
+ feature_high);<br>
+ if (ret)<br>
+ return ret;<br>
+ }<br>
+<br>
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
+ if (ret)<br>
+ return ret;<br>
+<br>
+ mutex_lock(&feature->mutex);<br>
+ bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,<br>
+ feature->feature_num);<br>
+ mutex_unlock(&feature->mutex);<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+static int navi10_set_ppfeature_status(struct smu_context *smu,<br>
+ uint64_t new_ppfeature_masks)<br>
+{<br>
+ uint64_t features_enabled;<br>
+ uint32_t feature_mask[2];<br>
+ uint64_t features_to_enable;<br>
+ uint64_t features_to_disable;<br>
+ int ret = 0;<br>
+<br>
+ ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
+ PP_ASSERT_WITH_CODE(!ret,<br>
+ "[SetPPfeatureStatus] Failed to get enabled smc features!",<br>
+ return ret);<br>
+ features_enabled = (uint64_t)feature_mask[0] |<br>
+ (uint64_t)feature_mask[1] << 32;<br>
+<br>
+ features_to_disable =<br>
+ features_enabled & ~new_ppfeature_masks;<br>
+ features_to_enable =<br>
+ ~features_enabled & new_ppfeature_masks;<br>
+<br>
+ pr_debug("features_to_disable 0x%llx\n", features_to_disable);<br>
+ pr_debug("features_to_enable 0x%llx\n", features_to_enable);<br>
+<br>
+ if (features_to_disable) {<br>
+ ret = navi10_enable_smc_features(smu, false, features_to_disable);<br>
+ PP_ASSERT_WITH_CODE(!ret,<br>
+ "[SetPPfeatureStatus] Failed to disable smc features!",<br>
+ return ret);<br>
+ }<br>
+<br>
+ if (features_to_enable) {<br>
+ ret = navi10_enable_smc_features(smu, true, features_to_enable);<br>
+ PP_ASSERT_WITH_CODE(!ret,<br>
+ "[SetPPfeatureStatus] Failed to enable smc features!",<br>
+ return ret);<br>
+ }<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
static const struct pptable_funcs navi10_ppt_funcs = {<br>
.tables_init = navi10_tables_init,<br>
.alloc_dpm_context = navi10_allocate_dpm_context,<br>
@@ -1308,6 +1471,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {<br>
.set_watermarks_table = navi10_set_watermarks_table,<br>
.read_sensor = navi10_read_sensor,<br>
.get_uclk_dpm_states = navi10_get_uclk_dpm_states,<br>
+ .get_ppfeature_status = navi10_get_ppfeature_status,<br>
+ .set_ppfeature_status = navi10_set_ppfeature_status,<br>
};<br>
<br>
void navi10_set_ppt_funcs(struct smu_context *smu)<br>
-- <br>
2.21.0<br>
<br>
_______________________________________________<br>
amd-gfx mailing list<br>
amd-gfx@lists.freedesktop.org<br>
<a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a></div>
</span></font></div>
</body>
</html>