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<p style="margin-top:0;margin-bottom:0">ping...,</p>
<p style="margin-top:0;margin-bottom:0">which one can help me review this patch.</p>
<p style="margin-top:0;margin-bottom:0">thanks.</p>
<p style="margin-top:0;margin-bottom:0"><br>
</p>
<p style="margin-top:0;margin-bottom:0">Best Regards,</p>
<p style="margin-top:0;margin-bottom:0">Kevin</p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Wang, Kevin(Yang)<br>
<b>Sent:</b> Wednesday, July 3, 2019 11:09:45 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhang, Hawking; Xiao, Jack; Huang, Ray; Wang, Kevin(Yang)<br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: add baco smu reset function for smu11</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">add baco reset support for smu11.<br>
it can help gpu do asic reset when gpu recovery.<br>
<br>
Change-Id: I7714ed03ad87c13e93ca1a7e6aef81eba14667c8<br>
Signed-off-by: Kevin Wang <kevin1.wang@amd.com><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c        |  6 +-<br>
 drivers/gpu/drm/amd/amdgpu/nv.c               |  9 +-<br>
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 14 +++<br>
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 26 ++++++<br>
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  8 ++<br>
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  8 ++<br>
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 91 +++++++++++++++++++<br>
 7 files changed, 159 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
index b41169261f7d..45dd22a1ef77 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
@@ -244,8 +244,10 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev,<br>
         mutex_lock(&adev->mman.gtt_window_lock);<br>
 <br>
         gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0);<br>
-       if (!adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||<br>
-           adev->asic_type != CHIP_NAVI10) {<br>
+       if (!adev->mman.buffer_funcs_enabled ||<br>
+           !adev->ib_pool_ready ||<br>
+           adev->asic_type != CHIP_NAVI10 ||<br>
+           adev->in_gpu_reset) {<br>
                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0);<br>
                 mutex_unlock(&adev->mman.gtt_window_lock);<br>
                 return;<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c<br>
index 8f605417b40a..cc5d06718e4c 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/nv.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c<br>
@@ -31,6 +31,7 @@<br>
 #include "amdgpu_vce.h"<br>
 #include "amdgpu_ucode.h"<br>
 #include "amdgpu_psp.h"<br>
+#include "amdgpu_smu.h"<br>
 #include "atom.h"<br>
 #include "amd_pcie.h"<br>
 <br>
@@ -266,8 +267,14 @@ static int nv_asic_reset(struct amdgpu_device *adev)<br>
 <br>
         amdgpu_atombios_scratch_regs_engine_hung(adev, false);<br>
 #endif<br>
+       int ret = 0;<br>
+       struct smu_context *smu = &adev->smu;<br>
 <br>
-       return 0;<br>
+       if (smu_baco_is_support(smu)) {<br>
+               ret = smu_baco_reset(smu);<br>
+       }<br>
+<br>
+       return ret;<br>
 }<br>
 <br>
 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)<br>
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
index b28a923f998d..fc416c686151 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
@@ -633,6 +633,11 @@ static int smu_sw_init(void *handle)<br>
         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);<br>
         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);<br>
         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);<br>
+<br>
+       mutex_init(&smu->smu_baco.mutex);<br>
+       smu->smu_baco.state = SMU_BACO_STATE_EXIT;<br>
+       smu->smu_baco.platform_support = false;<br>
+<br>
         smu->watermarks_bitmap = 0;<br>
         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;<br>
         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;<br>
@@ -1057,11 +1062,20 @@ static int smu_suspend(void *handle)<br>
         int ret;<br>
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
         struct smu_context *smu = &adev->smu;<br>
+       bool baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);<br>
 <br>
         ret = smu_system_features_control(smu, false);<br>
         if (ret)<br>
                 return ret;<br>
 <br>
+       if (adev->in_gpu_reset && baco_feature_is_enabled) {<br>
+               ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);<br>
+               if (ret) {<br>
+                       pr_warn("set BACO feature enabled failed, return %d\n", ret);<br>
+                       return ret;<br>
+               }<br>
+       }<br>
+<br>
         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);<br>
 <br>
         if (adev->asic_type >= CHIP_NAVI10 &&<br>
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
index 2818df46481c..c97324ef7db2 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
@@ -241,6 +241,7 @@ enum smu_message_type<br>
         SMU_MSG_PowerUpJpeg,<br>
         SMU_MSG_PowerDownJpeg,<br>
         SMU_MSG_BacoAudioD3PME,<br>
+       SMU_MSG_ArmD3,<br>
         SMU_MSG_MAX_COUNT,<br>
 };<br>
 <br>
@@ -489,6 +490,19 @@ struct mclock_latency_table {<br>
         struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];<br>
 };<br>
 <br>
+enum smu_baco_state<br>
+{<br>
+       SMU_BACO_STATE_ENTER = 0,<br>
+       SMU_BACO_STATE_EXIT,<br>
+};<br>
+<br>
+struct smu_baco_context<br>
+{<br>
+       struct mutex mutex;<br>
+       uint32_t state;<br>
+       bool platform_support;<br>
+};<br>
+<br>
 #define WORKLOAD_POLICY_MAX 7<br>
 struct smu_context<br>
 {<br>
@@ -505,6 +519,7 @@ struct smu_context<br>
         struct smu_power_context        smu_power;<br>
         struct smu_feature              smu_feature;<br>
         struct amd_pp_display_configuration  *display_config;<br>
+       struct smu_baco_context         smu_baco;<br>
         void *od_settings;<br>
 <br>
         uint32_t pstate_sclk;<br>
@@ -680,6 +695,11 @@ struct smu_funcs<br>
         int (*register_irq_handler)(struct smu_context *smu);<br>
         int (*set_azalia_d3_pme)(struct smu_context *smu);<br>
         int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);<br>
+       bool (*baco_is_support)(struct smu_context *smu);<br>
+       enum smu_baco_state (*baco_get_state)(struct smu_context *smu);<br>
+       int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);<br>
+       int (*baco_reset)(struct smu_context *smu);<br>
+<br>
 };<br>
 <br>
 #define smu_init_microcode(smu) \<br>
@@ -892,6 +912,12 @@ struct smu_funcs<br>
         ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)<br>
 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \<br>
         ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)<br>
+#define smu_baco_is_support(smu) \<br>
+       ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)<br>
+#define smu_baco_get_state(smu, state) \<br>
+       ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)<br>
+#define smu_baco_reset(smu) \<br>
+       ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)<br>
 <br>
 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,<br>
                                    uint16_t *size, uint8_t *frev, uint8_t *crev,<br>
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h<br>
index d93cd76269b4..2fff4b16cb4e 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h<br>
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h<br>
@@ -105,6 +105,14 @@ struct smu_11_0_power_context {<br>
         enum smu_11_0_power_state power_state;<br>
 };<br>
 <br>
+enum smu_v11_0_baco_seq {<br>
+       BACO_SEQ_BACO = 0,<br>
+       BACO_SEQ_MSR,<br>
+       BACO_SEQ_BAMACO,<br>
+       BACO_SEQ_ULPS,<br>
+       BACO_SEQ_COUNT,<br>
+};<br>
+<br>
 void smu_v11_0_set_smu_funcs(struct smu_context *smu);<br>
 <br>
 #endif<br>
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
index 373aeba44f16..7574a02350c6 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
@@ -115,6 +115,7 @@ static int navi10_message_map[SMU_MSG_MAX_COUNT] = {<br>
         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),<br>
         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),<br>
         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),<br>
+       MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),<br>
 };<br>
 <br>
 static int navi10_clk_map[SMU_CLK_COUNT] = {<br>
@@ -478,6 +479,7 @@ static int navi10_store_powerplay_table(struct smu_context *smu)<br>
 {<br>
         struct smu_11_0_powerplay_table *powerplay_table = NULL;<br>
         struct smu_table_context *table_context = &smu->smu_table;<br>
+       struct smu_baco_context *smu_baco = &smu->smu_baco;<br>
 <br>
         if (!table_context->power_play_table)<br>
                 return -EINVAL;<br>
@@ -489,6 +491,12 @@ static int navi10_store_powerplay_table(struct smu_context *smu)<br>
 <br>
         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;<br>
 <br>
+       mutex_lock(&smu_baco->mutex);<br>
+       if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||<br>
+           powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)<br>
+               smu_baco->platform_support = true;<br>
+       mutex_unlock(&smu_baco->mutex);<br>
+<br>
         return 0;<br>
 }<br>
 <br>
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c<br>
index ff047abd8d92..c6795de7177f 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c<br>
@@ -37,6 +37,7 @@<br>
 #include "asic_reg/mp/mp_11_0_offset.h"<br>
 #include "asic_reg/mp/mp_11_0_sh_mask.h"<br>
 #include "asic_reg/nbio/nbio_7_4_offset.h"<br>
+#include "asic_reg/nbio/nbio_7_4_sh_mask.h"<br>
 #include "asic_reg/smuio/smuio_11_0_0_offset.h"<br>
 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"<br>
 <br>
@@ -1637,6 +1638,92 @@ static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)<br>
         return ret;<br>
 }<br>
 <br>
+static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)<br>
+{<br>
+       return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);<br>
+}<br>
+<br>
+static bool smu_v11_0_baco_is_support(struct smu_context *smu)<br>
+{<br>
+       struct amdgpu_device *adev = smu->adev;<br>
+       struct smu_baco_context *smu_baco = &smu->smu_baco;<br>
+       uint32_t val;<br>
+       bool baco_support;<br>
+<br>
+       mutex_lock(&smu_baco->mutex);<br>
+       baco_support = smu_baco->platform_support;<br>
+       mutex_unlock(&smu_baco->mutex);<br>
+<br>
+       if (!baco_support)<br>
+               return false;<br>
+<br>
+       if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))<br>
+               return false;<br>
+<br>
+       val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);<br>
+       if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)<br>
+               return true;<br>
+<br>
+       return false;<br>
+}<br>
+<br>
+static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)<br>
+{<br>
+       struct smu_baco_context *smu_baco = &smu->smu_baco;<br>
+       enum smu_baco_state baco_state = SMU_BACO_STATE_EXIT;<br>
+<br>
+       mutex_lock(&smu_baco->mutex);<br>
+       baco_state = smu_baco->state;<br>
+       mutex_unlock(&smu_baco->mutex);<br>
+<br>
+       return baco_state;<br>
+}<br>
+<br>
+static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)<br>
+{<br>
+<br>
+       struct smu_baco_context *smu_baco = &smu->smu_baco;<br>
+       int ret = 0;<br>
+<br>
+       if (smu_v11_0_baco_get_state(smu) == state)<br>
+               return 0;<br>
+<br>
+       mutex_lock(&smu_baco->mutex);<br>
+<br>
+       if (state == SMU_BACO_STATE_ENTER)<br>
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);<br>
+       else<br>
+               ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);<br>
+       if (ret)<br>
+               goto out;<br>
+<br>
+       smu_baco->state = state;<br>
+out:<br>
+       mutex_unlock(&smu_baco->mutex);<br>
+       return ret;<br>
+}<br>
+<br>
+static int smu_v11_0_baco_reset(struct smu_context *smu)<br>
+{<br>
+       int ret = 0;<br>
+<br>
+       ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       msleep(10);<br>
+<br>
+       ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       return ret;<br>
+}<br>
+<br>
 static const struct smu_funcs smu_v11_0_funcs = {<br>
         .init_microcode = smu_v11_0_init_microcode,<br>
         .load_microcode = smu_v11_0_load_microcode,<br>
@@ -1685,6 +1772,10 @@ static const struct smu_funcs smu_v11_0_funcs = {<br>
         .register_irq_handler = smu_v11_0_register_irq_handler,<br>
         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,<br>
         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,<br>
+       .baco_is_support= smu_v11_0_baco_is_support,<br>
+       .baco_get_state = smu_v11_0_baco_get_state,<br>
+       .baco_set_state = smu_v11_0_baco_set_state,<br>
+       .baco_reset = smu_v11_0_baco_reset,<br>
 };<br>
 <br>
 void smu_v11_0_set_smu_funcs(struct smu_context *smu)<br>
-- <br>
2.22.0<br>
<br>
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