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<p style="margin-top:0;margin-bottom:0">okay, thanks.</p>
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<p style="margin-top:0;margin-bottom:0">Best Regards,</p>
<p style="margin-top:0;margin-bottom:0">Kevin</p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zhang, Hawking<br>
<b>Sent:</b> Friday, July 5, 2019 1:02:08 PM<br>
<b>To:</b> Wang, Kevin(Yang); amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Xiao, Jack; Kenenth.Feng@amd.com<br>
<b>Subject:</b> RE: [PATCH] drm/amdgpu: add mode1 (psp) reset for navi asic</font>
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<div class="PlainText"> if (smu_baco_is_support(smu)) {<br>
ret = smu_baco_reset(smu);<br>
+ } else {<br>
+ ret = nv_asic_mode1_reset(adev);<br>
}<br>
We don’t need {} for single statements. With that fixed, the patch is<br>
<br>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com><br>
<br>
Regards,<br>
Hawking<br>
<br>
-----Original Message-----<br>
From: Wang, Kevin(Yang) <Kevin1.Wang@amd.com> <br>
Sent: 2019年7月5日 12:58<br>
To: amd-gfx@lists.freedesktop.org<br>
Cc: Xiao, Jack <Jack.Xiao@amd.com>; Kenenth.Feng@amd.com; Zhang, Hawking <Hawking.Zhang@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com><br>
Subject: [PATCH] drm/amdgpu: add mode1 (psp) reset for navi asic<br>
<br>
add mode1 (by psp) reset for navi asic.<br>
<br>
Change-Id: Id2e7cb11eb7026296d1488c7c39f895b100f206c<br>
Signed-off-by: Kevin Wang <kevin1.wang@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/nv.c | 35 +++++++++++++++++++++++++++++++++<br>
1 file changed, 35 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index f6f152e6ade4..05fd4736bc0c 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/nv.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c<br>
@@ -256,6 +256,39 @@ static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) } #endif<br>
<br>
+static int nv_asic_mode1_reset(struct amdgpu_device *adev) {<br>
+ u32 i;<br>
+ int ret = 0;<br>
+<br>
+ amdgpu_atombios_scratch_regs_engine_hung(adev, true);<br>
+<br>
+ dev_info(adev->dev, "GPU mode1 reset\n");<br>
+<br>
+ /* disable BM */<br>
+ pci_clear_master(adev->pdev);<br>
+<br>
+ pci_save_state(adev->pdev);<br>
+<br>
+ ret = psp_gpu_reset(adev);<br>
+ if (ret)<br>
+ dev_err(adev->dev, "GPU mode1 reset failed\n");<br>
+<br>
+ pci_restore_state(adev->pdev);<br>
+<br>
+ /* wait for asic to come out of reset */<br>
+ for (i = 0; i < adev->usec_timeout; i++) {<br>
+ u32 memsize = adev->nbio_funcs->get_memsize(adev);<br>
+<br>
+ if (memsize != 0xffffffff)<br>
+ break;<br>
+ udelay(1);<br>
+ }<br>
+<br>
+ amdgpu_atombios_scratch_regs_engine_hung(adev, false);<br>
+<br>
+ return ret;<br>
+}<br>
static int nv_asic_reset(struct amdgpu_device *adev) {<br>
<br>
@@ -272,6 +305,8 @@ static int nv_asic_reset(struct amdgpu_device *adev)<br>
<br>
if (smu_baco_is_support(smu)) {<br>
ret = smu_baco_reset(smu);<br>
+ } else {<br>
+ ret = nv_asic_mode1_reset(adev);<br>
}<br>
<br>
return ret;<br>
--<br>
2.22.0<br>
<br>
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