<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> thanks, <div>i will make a new patch to fix this problem.</div> <div><br> </div> <div>Best Regards,</div> <div>Kevin</div> </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Quan, Evan<br> <b>Sent:</b> Friday, July 12, 2019 3:09:54 PM<br> <b>To:</b> Wang, Kevin(Yang); amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Feng, Kenneth<br> <b>Subject:</b> RE: [PATCH 3/3] drm/amd/powerplay: avoid double check feature enabled</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">Patch1 & 2 are reviewed-by: Evan Quan <evan.quan@amd.com><br> <br> For patch3, for dpm disabled case, "smu_get_dpm_freq_range(smu, clk_type, &min_freq,&max_freq)" will not se the min_freq and max_freq.<br> That will cause some troubles for the succeeding smu_set_soft_freq_range. Please get that handled properly.<br> <br> Regards,<br> Evan<br> > -----Original Message-----<br> > From: Wang, Kevin(Yang) <Kevin1.Wang@amd.com><br> > Sent: Friday, July 12, 2019 3:00 PM<br> > To: amd-gfx@lists.freedesktop.org<br> > Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Quan, Evan<br> > <Evan.Quan@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com><br> > Subject: [PATCH 3/3] drm/amd/powerplay: avoid double check feature<br> > enabled<br> > <br> > the unforce_dpm_levels doesn't need to check feature enable, because the<br> > smu_get_dpm_freq_range function has check feature logic.<br> > <br> > Change-Id: I6ae62b355aa76a00f0f6e164cd9848fb32fc7c12<br> > Signed-off-by: Kevin Wang <kevin1.wang@amd.com><br> > ---<br> > drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++++++++--------------<br> > 1 file changed, 8 insertions(+), 15 deletions(-)<br> > <br> > diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br> > b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br> > index 16a4c1ca98cf..895a4e592d5a 100644<br> > --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br> > +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br> > @@ -833,27 +833,20 @@ static int navi10_force_dpm_limit_value(struct<br> > smu_context *smu, bool highest)<br> > return ret;<br> > }<br> > <br> > -static int navi10_unforce_dpm_levels(struct smu_context *smu) {<br> > -<br> > +static int navi10_unforce_dpm_levels(struct smu_context *smu) {<br> > int ret = 0, i = 0;<br> > uint32_t min_freq, max_freq;<br> > enum smu_clk_type clk_type;<br> > <br> > - struct clk_feature_map {<br> > - enum smu_clk_type clk_type;<br> > - uint32_t feature;<br> > - } clk_feature_map[] = {<br> > - {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},<br> > - {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},<br> > - {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},<br> > + enum smu_clk_type clks[] = {<br> > + SMU_GFXCLK,<br> > + SMU_MCLK,<br> > + SMU_SOCCLK,<br> > };<br> > <br> > - for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {<br> > - if (!smu_feature_is_enabled(smu,<br> > clk_feature_map[i].feature))<br> > - continue;<br> > -<br> > - clk_type = clk_feature_map[i].clk_type;<br> > -<br> > + for (i = 0; i < ARRAY_SIZE(clks); i++) {<br> > + clk_type = clks[i];<br> > ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,<br> > &max_freq);<br> > if (ret)<br> > return ret;<br> > --<br> > 2.22.0<br> <br> </div> </span></font></div> </body> </html>