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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Russell, Kent <Kent.Russell@amd.com><br>
<b>Sent:</b> Monday, July 15, 2019 8:54 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Russell, Kent<br>
<b>Subject:</b> [PATCH] drm/amdgpu: Fix Vega20 Perf counter for pcie_bw</font>
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<div class="PlainText">The perf counter for Vega20 is 108, instead of 104 which it was on all<br>
previous GPUs, so add a check to use the appropriate value.<br>
<br>
Change-Id: Id5b5026a03b09d8b9d52dda85e17ed5acd818912<br>
Signed-off-by: Kent Russell <kent.russell@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++++++++--<br>
1 file changed, 8 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c<br>
index 1e424d918334..852ad0a07995 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c<br>
@@ -716,9 +716,15 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,<br>
return;<br>
<br>
/* Set the 2 events that we wish to watch, defined above */<br>
- /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */<br>
+ /* Reg 40 is # received msgs */<br>
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);<br>
- perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);<br>
+ /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */<br>
+ if (adev->asic_type == CHIP_VEGA20)<br>
+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,<br>
+ EVENT1_SEL, 108);<br>
+ else<br>
+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,<br>
+ EVENT1_SEL, 104);<br>
<br>
/* Write to enable desired perf counters */<br>
WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);<br>
-- <br>
2.17.1<br>
<br>
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