<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style> </head> <body dir="ltr"> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Sure. That makes more sense. We should switch raven to use it as well.</div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Alex </div> <div id="appendonsend"></div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">From: Quan, Evan Sent: Friday, July 19, 2019 5:47 AM To: amd-gfx@lists.freedesktop.org; Deucher, Alexander Subject: RE: [PATCH] drm/amd/powerplay: correct the bit mask for checking VCN power status <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">Considering this is actually different from traditional UVD, maybe it's better to add a new flag like AMDGPU_PP_SENSOR_VCN_POWER. @Deucher, Alexander any comment? Regards, Evan > -----Original Message----- > From: Huang, Ray <Ray.Huang@amd.com> > Sent: Friday, July 19, 2019 5:21 PM > To: Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Quan, Evan <Evan.Quan@amd.com> > Subject: RE: [PATCH] drm/amd/powerplay: correct the bit mask for checking > VCN power status > > > -----Original Message----- > > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > > Evan Quan > > Sent: Friday, July 19, 2019 4:52 PM > > To: amd-gfx@lists.freedesktop.org > > Cc: Quan, Evan <Evan.Quan@amd.com> > > Subject: [PATCH] drm/amd/powerplay: correct the bit mask for checking > > VCN power status > > > > For Navi10 or later ASICs, a different bit mask is used for checking > > VCN power status. > > > > Change-Id: Iaa49e5a339c38f46e3e7124d21aeb65f6633325e > > Signed-off-by: Evan Quan <evan.quan@amd.com> > > --- > > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > index 6e2f7df826f0..887577c47568 100644 > > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > > @@ -271,6 +271,8 @@ int smu_get_power_num_states(struct > smu_context > > *smu, int smu_common_read_sensor(struct smu_context *smu, enum > > amd_pp_sensors sensor, > > void *data, uint32_t *size) > > { > > + struct amdgpu_device *adev = smu->adev; > > + uint32_t uvd_bit_mask = 0xFFFFFFFF; > > int ret = 0; > > > > switch (sensor) { > > @@ -287,7 +289,11 @@ int smu_common_read_sensor(struct > smu_context > > *smu, enum amd_pp_sensors sensor, > > *size = 8; > > break; > > case AMDGPU_PP_SENSOR_UVD_POWER: > > - *(uint32_t *)data = smu_feature_is_enabled(smu, > > SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; > > + if (adev->asic_type == CHIP_VEGA20) > > + uvd_bit_mask = SMU_FEATURE_DPM_UVD_BIT; > > + else > > + uvd_bit_mask = SMU_FEATURE_VCN_PG_BIT; > > After vega20, we actually will use VCN instead of UVD. Below indicates the > design for this. > > uvd_bit_mask = (adev->asic_type > CHIP_VEGA20) ? > SMU_FEATURE_VCN_PG_BIT : SMU_FEATURE_DPM_UVD_BIT > > Anyway, patch looks good for me. > Reviewed-by: Huang Rui <ray.huang@amd.com> > > > Thanks, > Ray > > > + *(uint32_t *)data = smu_feature_is_enabled(smu, > > uvd_bit_mask) ? 1 : > > +0; > > *size = 4; > > break; > > case AMDGPU_PP_SENSOR_VCE_POWER: > > -- > > 2.22.0 > > > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a> </div> </div> </body> </html>