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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">Parameter 0xff for message PPSMC_MSG_GetDpmFreqByIndex will get the dpm numbers, so it’s ok.<o:p></o:p></span></p>
<p class="MsoPlainText">Reviewed-by: Kenneth Feng <<a href="mailto:kenneth.feng@amd.com">kenneth.feng@amd.com</a>><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Wang, Kevin(Yang)
<br>
<b>Sent:</b> Friday, July 19, 2019 1:36 PM<br>
<b>To:</b> Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Feng, Kenneth <Kenneth.Feng@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Gui, Jack <Jack.Gui@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">Comment inline</span><span style="font-family:"Calibri",sans-serif;color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Quan, Evan <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>><br>
<b>Sent:</b> Friday, July 19, 2019 1:03 PM<br>
<b>To:</b> Wang, Kevin(Yang) <<a href="mailto:Kevin1.Wang@amd.com">Kevin1.Wang@amd.com</a>>;
<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Cc:</b> Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>>; Huang, Ray <<a href="mailto:Ray.Huang@amd.com">Ray.Huang@amd.com</a>>; Xu, Feifei <<a href="mailto:Feifei.Xu@amd.com">Feifei.Xu@amd.com</a>>; Gui, Jack <<a href="mailto:Jack.Gui@amd.com">Jack.Gui@amd.com</a>><br>
<b>Subject:</b> RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10</span><span style="font-family:"Calibri",sans-serif;color:black">
<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Calibri",sans-serif;color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">Comment inline<br>
<br>
> -----Original Message-----<br>
> From: Wang, Kevin(Yang) <<a href="mailto:Kevin1.Wang@amd.com">Kevin1.Wang@amd.com</a>><br>
> Sent: Friday, July 19, 2019 11:46 AM<br>
> To: <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
> Cc: Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>>; Quan, Evan<br>
> <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>>; Huang, Ray <<a href="mailto:Ray.Huang@amd.com">Ray.Huang@amd.com</a>>; Xu, Feifei<br>
> <<a href="mailto:Feifei.Xu@amd.com">Feifei.Xu@amd.com</a>>; Gui, Jack <<a href="mailto:Jack.Gui@amd.com">Jack.Gui@amd.com</a>>; Wang, Kevin(Yang)<br>
> <<a href="mailto:Kevin1.Wang@amd.com">Kevin1.Wang@amd.com</a>><br>
> Subject: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10<br>
> <br>
> 1.NAVI10_PEAK_SCLK_XTX    1830 Mhz<br>
> 2.NAVI10_PEAK_SCLK_XT     1755 Mhz<br>
> 3.NAVI10_PEAK_SCLK_XL     1625 Mhz<br>
> <br>
> Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6<br>
> Signed-off-by: Kevin Wang <<a href="mailto:kevin1.wang@amd.com">kevin1.wang@amd.com</a>><br>
> ---<br>
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 65 ++++++++++--------<br>
> -<br>
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 ++<br>
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 55 ++++++++++++++++<br>
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.h    |  4 ++<br>
>  4 files changed, 97 insertions(+), 31 deletions(-)<br>
> <br>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
> index 7f51bbd2ac90..ab389dde9562 100644<br>
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
> @@ -1360,37 +1360,40 @@ int smu_adjust_power_state_dynamic(struct<br>
> smu_context *smu,<br>
>        }<br>
> <br>
>        if (smu_dpm_ctx->dpm_level != level) {<br>
> -             switch (level) {<br>
> -             case AMD_DPM_FORCED_LEVEL_HIGH:<br>
> -                     ret = smu_force_dpm_limit_value(smu, true);<br>
> -                     break;<br>
> -             case AMD_DPM_FORCED_LEVEL_LOW:<br>
> -                     ret = smu_force_dpm_limit_value(smu, false);<br>
> -                     break;<br>
> -<br>
> -             case AMD_DPM_FORCED_LEVEL_AUTO:<br>
> -             case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:<br>
> -                     ret = smu_unforce_dpm_levels(smu);<br>
> -                     break;<br>
> -<br>
> -             case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:<br>
> -             case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:<br>
> -             case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:<br>
> -                     ret = smu_get_profiling_clk_mask(smu, level,<br>
> -                                                      &sclk_mask,<br>
> -                                                      &mclk_mask,<br>
> -                                                      &soc_mask);<br>
> -                     if (ret)<br>
> -                             return ret;<br>
> -                     smu_force_clk_levels(smu, SMU_SCLK, 1 <<<br>
> sclk_mask);<br>
> -                     smu_force_clk_levels(smu, SMU_MCLK, 1 <<<br>
> mclk_mask);<br>
> -                     smu_force_clk_levels(smu, SMU_SOCCLK, 1 <<<br>
> soc_mask);<br>
> -                     break;<br>
> -<br>
> -             case AMD_DPM_FORCED_LEVEL_MANUAL:<br>
> -             case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:<br>
> -             default:<br>
> -                     break;<br>
> +             ret = smu_set_performance_level(smu, level);<br>
> +             if (ret) {<br>
[Quan, Evan] Since this actually handles AMD_DPM_FORCED_LEVEL_PROFILE_PEAK only. Please move this under "case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:".<br>
And please give it a more meaningful name e.g. smu_set_asic_peak_profile().<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">[kevin]: in the future, for specifc asic, it may be custom other performance level, so we should have this capacity to support other asic with any performance level. and
 i think it is not a good way to handle performance level use case by case method for each asic.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"><br>
> +                     switch (level) {<br>
> +                     case AMD_DPM_FORCED_LEVEL_HIGH:<br>
> +                             ret = smu_force_dpm_limit_value(smu, true);<br>
> +                             break;<br>
> +                     case AMD_DPM_FORCED_LEVEL_LOW:<br>
> +                             ret = smu_force_dpm_limit_value(smu,<br>
> false);<br>
> +                             break;<br>
> +<br>
> +                     case AMD_DPM_FORCED_LEVEL_AUTO:<br>
> +                     case<br>
> AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:<br>
> +                             ret = smu_unforce_dpm_levels(smu);<br>
> +                             break;<br>
> +<br>
> +                     case<br>
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:<br>
> +                     case<br>
> AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:<br>
> +                     case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:<br>
> +                             ret = smu_get_profiling_clk_mask(smu, level,<br>
> +                                                              &sclk_mask,<br>
> +                                                              &mclk_mask,<br>
> +                                                              &soc_mask);<br>
> +                             if (ret)<br>
> +                                     return ret;<br>
> +                             smu_force_clk_levels(smu, SMU_SCLK, 1 <<<br>
> sclk_mask);<br>
> +                             smu_force_clk_levels(smu, SMU_MCLK, 1 <<<br>
> mclk_mask);<br>
> +                             smu_force_clk_levels(smu, SMU_SOCCLK, 1<br>
> << soc_mask);<br>
> +                             break;<br>
> +<br>
> +                     case AMD_DPM_FORCED_LEVEL_MANUAL:<br>
> +                     case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:<br>
> +                     default:<br>
> +                             break;<br>
> +                     }<br>
>                }<br>
> <br>
>                if (!ret)<br>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
> index 514d31518853..ba5ddafcbdba 100644<br>
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
> @@ -631,6 +631,7 @@ struct pptable_funcs {<br>
>        int (*get_thermal_temperature_range)(struct smu_context *smu,<br>
> struct smu_temperature_range *range);<br>
>        int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t<br>
> *clocks_in_khz, uint32_t *num_states);<br>
>        int (*set_default_od_settings)(struct smu_context *smu, bool<br>
> initialize);<br>
> +     int (*set_performance_level)(struct smu_context *smu, int32_t<br>
> level);<br>
>  };<br>
> <br>
>  struct smu_funcs<br>
> @@ -928,6 +929,9 @@ struct smu_funcs<br>
>        ((smu)->funcs->baco_get_state? (smu)->funcs-<br>
> >baco_get_state((smu), (state)) : 0)<br>
>  #define smu_baco_reset(smu) \<br>
>        ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)<br>
> +#define smu_set_performance_level(smu, level) \<br>
> +     ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs-<br>
> >set_performance_level((smu), (level)) : -EINVAL);<br>
> +<br>
> <br>
>  extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t<br>
> table,<br>
>                                   uint16_t *size, uint8_t *frev, uint8_t *crev,<br>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
> index e44041a25e64..9024d91477f0 100644<br>
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
> @@ -1590,6 +1590,60 @@ static int navi10_set_ppfeature_status(struct<br>
> smu_context *smu,<br>
>        return 0;<br>
>  }<br>
> <br>
> +static int navi10_set_peak_clock_by_device(struct smu_context *smu)<br>
> +{<br>
> +     struct amdgpu_device *adev = smu->adev;<br>
> +     int ret = 0;<br>
> +     uint32_t sclk_freq = 0, uclk_freq = 0;<br>
> +     uint32_t uclk_level = 0;<br>
> +<br>
> +     switch (adev->rev_id) {<br>
> +     case 0xf0: /* XTX */<br>
> +     case 0xC0:<br>
> +             sclk_freq = NAVI10_PEAK_SCLK_XTX;<br>
> +             break;<br>
> +     case 0xf1: /* XT */<br>
> +     case 0xC1:<br>
> +             sclk_freq = NAVI10_PEAK_SCLK_XT;<br>
> +             break;<br>
> +     default: /* XL */<br>
> +             sclk_freq = NAVI10_PEAK_SCLK_XL;<br>
> +             break;<br>
> +     }<br>
> +<br>
> +     ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);<br>
> +     if (ret)<br>
> +             return ret;<br>
> +     ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1,<br>
> &uclk_freq);<br>
> +     if (ret)<br>
> +             return ret;<br>
[Quan, Evan] I think with dpm level (3rd argument) set as 0xff directly,  you can  get the clock frequency for the max level.<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">[kevin]: not right, 0xff will return dpm clock level count, see function smu_get_dpm_level_count <br>
> +<br>
> +     ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq,<br>
> sclk_freq);<br>
> +     if (ret)<br>
> +             return ret;<br>
> +     ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq,<br>
> uclk_freq);<br>
> +     if (ret)<br>
> +             return ret;<br>
> +<br>
> +     return ret;<br>
> +}<br>
> +<br>
> +static int navi10_set_performance_level(struct smu_context *smu, int32_t<br>
> level)<br>
> +{<br>
> +     int ret = 0;<br>
> +<br>
> +     switch (level) {<br>
> +     case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:<br>
> +             ret = navi10_set_peak_clock_by_device(smu);<br>
> +             break;<br>
> +     default:<br>
> +             ret = -EINVAL;<br>
> +             break;<br>
> +     }<br>
> +<br>
> +     return ret;<br>
> +}<br>
> +<br>
>  static const struct pptable_funcs navi10_ppt_funcs = {<br>
>        .tables_init = navi10_tables_init,<br>
>        .alloc_dpm_context = navi10_allocate_dpm_context,<br>
> @@ -1625,6 +1679,7 @@ static const struct pptable_funcs navi10_ppt_funcs<br>
> = {<br>
>        .get_uclk_dpm_states = navi10_get_uclk_dpm_states,<br>
>        .get_ppfeature_status = navi10_get_ppfeature_status,<br>
>        .set_ppfeature_status = navi10_set_ppfeature_status,<br>
> +     .set_performance_level = navi10_set_performance_level,<br>
>  };<br>
> <br>
>  void navi10_set_ppt_funcs(struct smu_context *smu)<br>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h<br>
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h<br>
> index 957288e22f47..620ff17c2fef 100644<br>
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h<br>
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h<br>
> @@ -23,6 +23,10 @@<br>
>  #ifndef __NAVI10_PPT_H__<br>
>  #define __NAVI10_PPT_H__<br>
> <br>
> +#define NAVI10_PEAK_SCLK_XTX         (1830)<br>
> +#define NAVI10_PEAK_SCLK_XT           (1755)<br>
> +#define NAVI10_PEAK_SCLK_XL           (1625)<br>
> +<br>
>  extern void navi10_set_ppt_funcs(struct smu_context *smu);<br>
> <br>
>  #endif<br>
> --<br>
> 2.22.0<o:p></o:p></span></p>
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