<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> <p style="margin-top:0;margin-bottom:0"></p> <div>It's not necessary in the current code, </div> <div>but if you update the implementation of the API one day, </div> <div>your code won't look so strong. <div>I don't recommend it.</div> </div> <div><br> </div> <div>Best Regards,<br> Kevin</div> <br> <p></p> </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Quan, Evan <Evan.Quan@amd.com><br> <b>Sent:</b> Monday, July 22, 2019 2:42:26 PM<br> <b>To:</b> Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br> <b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br> <b>Subject:</b> RE: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control</font> <div> </div> </div> <style>  </style> <div lang="EN-US" link="blue" vlink="purple"> <div class="x_WordSection1"> <p class="x_MsoNormal">That does not really matters. The API will still return success even on <span style="font-family:"Segoe UI",sans-serif; color:#212121">smu_feature_set_enabled failure. It does not care about smu_feature_set_enabled failure.</span></p> <p class="x_MsoNormal">But it helps me find another issue(about the naming smu_feature_set_enabled). I just sent out a patch to address that.</p> <p class="x_MsoNormal"> </p> <p class="x_MsoNormal">Regards,</p> <p class="x_MsoNormal">Evan</p> <div style="border:none; border-left:solid blue 1.5pt; padding:0in 0in 0in 4.0pt"> <div> <div style="border:none; border-top:solid #E1E1E1 1.0pt; padding:3.0pt 0in 0in 0in"> <p class="x_MsoNormal"><b>From:</b> Wang, Kevin(Yang) <Kevin1.Wang@amd.com> <br> <b>Sent:</b> Monday, July 22, 2019 1:39 PM<br> <b>To:</b> Feng, Kenneth <Kenneth.Feng@amd.com>; Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br> <b>Subject:</b> Re: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control</p> </div> </div> <p class="x_MsoNormal"> </p> <div id="x_divtagdefaultwrapper"> <p><span style="font-size:12.0pt; color:black">you should check return value in smu anytime.</span></p> <p><span style="font-size:12.0pt; color:black"> </span></p> <p><span style="font-family:"Segoe UI",sans-serif; color:#212121">+ smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);<br> +</span><span style="font-size:12.0pt; color:black"></span></p> <p><span style="font-size:12.0pt; color:black"> </span></p> <p><span style="font-size:12.0pt; color:black">Reviewed-by: Kevin Wang <<a href="mailto:kevin1.wang@amd.com">kevin1.wang@amd.com</a>></span></p> <p><span style="font-size:12.0pt; color:black"> </span></p> <p><span style="font-size:12.0pt; color:black">Best Regards,<br> kevin</span></p> </div> <div class="x_MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="x_divRplyFwdMsg"> <p class="x_MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>><br> <b>Sent:</b> Monday, July 22, 2019 12:28:40 PM<br> <b>To:</b> Quan, Evan <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br> <b>Cc:</b> Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>>; Quan, Evan <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>><br> <b>Subject:</b> RE: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control</span> </p> <div> <p class="x_MsoNormal"> </p> </div> </div> <div> <div> <p class="x_MsoNormal">Reviewed-by: Kenneth Feng <<a href="mailto:kenneth.feng@amd.com">kenneth.feng@amd.com</a>><br> <br> <br> -----Original Message-----<br> From: amd-gfx [<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">mailto:amd-gfx-bounces@lists.freedesktop.org</a>] On Behalf Of Evan Quan<br> Sent: Monday, July 22, 2019 11:16 AM<br> To: <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> Cc: Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>>; Quan, Evan <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>><br> Subject: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control<br> <br> [CAUTION: External Email]<br> <br> No VCN DPM bit check as that's different from VCN PG. Also no extra check for possible double enablement/disablement as that's already done by VCN.<br> <br> Change-Id: I59c63829cf4dcb8093fde1ca8245b613ab2d90df<br> Signed-off-by: Evan Quan <<a href="mailto:evan.quan@amd.com">evan.quan@amd.com</a>><br> ---<br> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 ++++++++--------------<br> 1 file changed, 9 insertions(+), 17 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br> index c8ce9bbae276..2198d373d38c 100644<br> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br> @@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) {<br> int ret = 0;<br> - struct smu_power_context *smu_power = &smu->smu_power;<br> - struct smu_power_gate *power_gate = &smu_power->power_gate;<br> <br> - if (enable && power_gate->uvd_gated) {<br> - if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {<br> - ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);<br> - if (ret)<br> - return ret;<br> - }<br> - power_gate->uvd_gated = false;<br> + if (enable) {<br> + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);<br> + if (ret)<br> + return ret;<br> } else {<br> - if (!enable && !power_gate->uvd_gated) {<br> - if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {<br> - ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);<br> - if (ret)<br> - return ret;<br> - }<br> - power_gate->uvd_gated = true;<br> - }<br> + ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);<br> + if (ret)<br> + return ret;<br> }<br> <br> + smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);<br> +<br> return 0;<br> }<br> <br> --<br> 2.22.0<br> <br> _______________________________________________<br> amd-gfx mailing list<br> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> _______________________________________________<br> amd-gfx mailing list<br> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a></p> </div> </div> </div> </div> </div> </body> </html>