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Tom, does umr use it?</div>
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Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Huang, Ray <Ray.Huang@amd.com><br>
<b>Sent:</b> Thursday, July 25, 2019 4:49 AM<br>
<b>To:</b> Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Cc:</b> Feng, Kenneth <Kenneth.Feng@amd.com><br>
<b>Subject:</b> RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu</font>
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<p class="x_MsoNormal">Any other user mode tool use the “ppfeature” sysfs interface?</p>
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<p class="x_MsoNormal">Thanks,</p>
<p class="x_MsoNormal">Ray</p>
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<p class="x_MsoNormal"><b>From:</b> Wang, Kevin(Yang) <Kevin1.Wang@amd.com> <br>
<b>Sent:</b> Thursday, July 25, 2019 4:44 PM<br>
<b>To:</b> Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Cc:</b> Huang, Ray <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com><br>
<b>Subject:</b> Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu</p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">in fact, i don't want to change this sysfs name from "ppfeatures" to "pp_features", </span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">but it seems that don't have same name format with other pp sysfs node.</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">the other powerplay sysfs name have "pp_" prefix, i think we'd better to change it name to "pp_features"</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">eg:</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk  pp_force_state  pp_num_states          pp_sclk_od<br>
pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od      pp_power_profile_mode  pp_table</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black"><a id="OWAAM782110" href="mailto:Alexander.Deucher@amd.com"><span style="font-family:"Calibri",sans-serif; text-decoration:none">@Deucher, Alexander</span></a> <a id="OWAAM387764" href="mailto:Hawking.Zhang@amd.com"><span style="font-family:"Calibri",sans-serif; text-decoration:none">@Zhang,
 Hawking</span></a></span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">Could you give us some idea about it,</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">Thanks.</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">Best Regards,<br>
Kevin</span></p>
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<p class="x_MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Quan, Evan <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>><br>
<b>Sent:</b> Thursday, July 25, 2019 4:30 PM<br>
<b>To:</b> Wang, Kevin(Yang) <<a href="mailto:Kevin1.Wang@amd.com">Kevin1.Wang@amd.com</a>>;
<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Cc:</b> Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>>; Huang, Ray <<a href="mailto:Ray.Huang@amd.com">Ray.Huang@amd.com</a>>; Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>><br>
<b>Subject:</b> RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu</span>
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<p class="x_xmsonormal">To keep backward compatibility, we cannot change the sysfs file naming.</p>
<p class="x_xmsonormal">But it’s a good idea to summarize these as common APIs.</p>
<p class="x_xmsonormal"> </p>
<p class="x_xmsonormal">Regards,</p>
<p class="x_xmsonormal">Evan</p>
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<p class="x_xmsonormal"><b>From:</b> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>>
<b>On Behalf Of </b>Wang, Kevin(Yang)<br>
<b>Sent:</b> Thursday, July 25, 2019 4:10 PM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<b>Cc:</b> Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>>; Huang, Ray <<a href="mailto:Ray.Huang@amd.com">Ray.Huang@amd.com</a>>; Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>><br>
<b>Subject:</b> Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu</p>
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<p class="x_xmsonormal"> </p>
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<p class="x_xmsonormal"><span style="font-size:12.0pt; color:black">add sample data from sysfs pp_features with this patch.</span></p>
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<p class="x_xmsonormal"><span style="font-size:12.0pt; color:black">print format:</span></p>
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<p class="x_xmsonormal"><span style="font-size:12.0pt; color:black">index. feature name (Hardware Message ID): state</span></p>
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<p class="x_xmsonormal"><i><span style="font-size:9.0pt; color:black">sudo find /sys -name "pp_features" -exec cat {} \;</span></i></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">features high: 0x00000623 low: 0xb3cdaffb</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">00. DPM_PREFETCHER       ( 0) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">01. DPM_GFXCLK           ( 1) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">02. DPM_UCLK             ( 3) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">03. DPM_SOCCLK           ( 4) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">04. DPM_MP0CLK           ( 5) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">05. DPM_LINK             ( 6) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">06. DPM_DCEFCLK          ( 7) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">07. DS_GFXCLK            (10) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">08. DS_SOCCLK            (11) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">09. DS_LCLK              (12) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">10. PPT                  (23) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">11. TDC                  (24) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">12. THERMAL              (33) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">13. RM                   (35) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">14. DS_DCEFCLK           (13) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">15. ACDC                 (28) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">16. VR0HOT               (29) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">17. VR1HOT               (30) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">18. FW_CTF               (31) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">19. LED_DISPLAY          (36) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">20. FAN_CONTROL          (32) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">21. GFX_EDC              (25) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">22. GFXOFF               (17) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">23. DPM_GFX_PACE         ( 2) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">24. MEM_VDDCI_SCALING    ( 8) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">25. MEM_MVDD_SCALING     ( 9) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">26. DS_UCLK              (14) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">27. GFX_ULV              (15) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">28. FW_DSTATE            (16) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">29. BACO                 (18) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">30. VCN_PG               (19) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">31. JPEG_PG              (20) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">32. USB_PG               (21) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">33. RSMU_SMN_CG          (22) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">34. APCC_PLUS            (26) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">35. GTHR                 (27) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">36. GFX_DCS              (34) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">37. GFX_SS               (37) : enabeld</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">38. OUT_OF_BAND_MONITOR  (38) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">39. TEMP_DEPENDENT_VMIN  (39) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">40. MMHUB_PG             (40) : disabled</span></p>
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<p class="x_xmsonormal"><span style="font-size:9.0pt; color:black">41. ATHUB_PG             (41) : enabeld</span></p>
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<p class="x_xmsonormal"><b><span style="color:black">From:</span></b><span style="color:black"> Wang, Kevin(Yang) <<a href="mailto:Kevin1.Wang@amd.com">Kevin1.Wang@amd.com</a>><br>
<b>Sent:</b> Thursday, July 25, 2019 1:11 PM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Cc:</b> Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>>; Huang, Ray <<a href="mailto:Ray.Huang@amd.com">Ray.Huang@amd.com</a>>; Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>>;
 Wang, Kevin(Yang) <<a href="mailto:Kevin1.Wang@amd.com">Kevin1.Wang@amd.com</a>><br>
<b>Subject:</b> [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu</span>
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<p class="x_xmsonormal" style="margin-bottom:12.0pt">1. Unified feature enable status format in sysfs<br>
2. Rename ppfeature to pp_features to adapt other pp sysfs node name<br>
3. this function support all asic, not asic related function.<br>
<br>
Signed-off-by: Kevin Wang <<a href="mailto:kevin1.wang@amd.com">kevin1.wang@amd.com</a>><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--<br>
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++<br>
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-<br>
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------<br>
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------<br>
 5 files changed, 75 insertions(+), 336 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
index 866097d5cf26..9e8e8a65d9bf 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,<br>
 }<br>
 <br>
 /**<br>
- * DOC: ppfeatures<br>
+ * DOC: pp_features<br>
  *<br>
  * The amdgpu driver provides a sysfs API for adjusting what powerplay<br>
- * features to be enabled. The file ppfeatures is used for this. And<br>
+ * features to be enabled. The file pp_features is used for this. And<br>
  * this is only available for Vega10 and later dGPUs.<br>
  *<br>
  * Reading back the file will show you the followings:<br>
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,<br>
  * the corresponding bit from original ppfeature masks and input the<br>
  * new ppfeature masks.<br>
  */<br>
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,<br>
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,<br>
                 struct device_attribute *attr,<br>
                 const char *buf,<br>
                 size_t count)<br>
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,<br>
         pr_debug("featuremask = 0x%llx\n", featuremask);<br>
 <br>
         if (is_support_sw_smu(adev)) {<br>
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);<br>
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);<br>
                 if (ret)<br>
                         return -EINVAL;<br>
         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {<br>
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,<br>
         return count;<br>
 }<br>
 <br>
-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,<br>
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,<br>
                 struct device_attribute *attr,<br>
                 char *buf)<br>
 {<br>
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,<br>
         struct amdgpu_device *adev = ddev->dev_private;<br>
 <br>
         if (is_support_sw_smu(adev)) {<br>
-               return smu_get_ppfeature_status(&adev->smu, buf);<br>
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);<br>
         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)<br>
                 return amdgpu_dpm_get_ppfeature_status(adev, buf);<br>
 <br>
@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,<br>
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,<br>
                 amdgpu_get_memory_busy_percent, NULL);<br>
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);<br>
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,<br>
-               amdgpu_get_ppfeature_status,<br>
-               amdgpu_set_ppfeature_status);<br>
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,<br>
+               amdgpu_get_pp_feature_status,<br>
+               amdgpu_set_pp_feature_status);<br>
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);<br>
 <br>
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,<br>
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)<br>
         if ((adev->asic_type >= CHIP_VEGA10) &&<br>
             !(adev->flags & AMD_IS_APU)) {<br>
                 ret = device_create_file(adev->dev,<br>
-                               &dev_attr_ppfeatures);<br>
+                               &dev_attr_pp_features);<br>
                 if (ret) {<br>
                         DRM_ERROR("failed to create device file "<br>
-                                       "ppfeatures\n");<br>
+                                       "pp_features\n");<br>
                         return ret;<br>
                 }<br>
         }<br>
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)<br>
                 device_remove_file(adev->dev, &dev_attr_unique_id);<br>
         if ((adev->asic_type >= CHIP_VEGA10) &&<br>
             !(adev->flags & AMD_IS_APU))<br>
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);<br>
+               device_remove_file(adev->dev, &dev_attr_pp_features);<br>
 }<br>
 <br>
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)<br>
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
index e881de955388..90833ff2fe00 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask<br>
         return __smu_feature_names[feature];<br>
 }<br>
 <br>
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)<br>
+{<br>
+       size_t size = 0;<br>
+       int ret = 0, i = 0;<br>
+       uint32_t feature_mask[2] = { 0 };<br>
+       int32_t feature_index = 0;<br>
+       uint32_t count = 0;<br>
+<br>
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
+       if (ret)<br>
+               goto failed;<br>
+<br>
+       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",<br>
+                       feature_mask[1], feature_mask[0]);<br>
+<br>
+       for (i = 0; i < SMU_FEATURE_COUNT; i++) {<br>
+               feature_index = smu_feature_get_index(smu, i);<br>
+               if (feature_index < 0)<br>
+                       continue;<br>
+               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",<br>
+                              count++,<br>
+                              smu_get_feature_name(smu, i),<br>
+                              feature_index,<br>
+                              !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");<br>
+       }<br>
+<br>
+failed:<br>
+       return size;<br>
+}<br>
+<br>
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)<br>
+{<br>
+       int ret = 0;<br>
+       uint32_t feature_mask[2] = { 0 };<br>
+       uint64_t feature_2_enabled = 0;<br>
+       uint64_t feature_2_disabled = 0;<br>
+       uint64_t feature_enables = 0;<br>
+<br>
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);<br>
+<br>
+       feature_2_enabled  = ~feature_enables & new_mask;<br>
+       feature_2_disabled = feature_enables & ~new_mask;<br>
+<br>
+       if (feature_2_enabled) {<br>
+               ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);<br>
+               if (ret)<br>
+                       ret;<br>
+       }<br>
+       if (feature_2_disabled) {<br>
+               ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);<br>
+               if (ret)<br>
+                       return ret;<br>
+       }<br>
+<br>
+       return ret;<br>
+}<br>
+<br>
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)<br>
 {<br>
         int ret = 0;<br>
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
index abc2644b4c07..ac9e9d5d8a5c 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h<br>
@@ -432,8 +432,6 @@ struct pptable_funcs {<br>
                                       uint32_t *mclk_mask,<br>
                                       uint32_t *soc_mask);<br>
         int (*set_cpu_power_state)(struct smu_context *smu);<br>
-       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);<br>
-       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);<br>
         bool (*is_dpm_running)(struct smu_context *smu);<br>
         int (*tables_init)(struct smu_context *smu, struct smu_table *tables);<br>
         int (*set_thermal_fan_table)(struct smu_context *smu);<br>
@@ -713,10 +711,6 @@ struct smu_funcs<br>
         ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)<br>
 #define smu_set_xgmi_pstate(smu, pstate) \<br>
                 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)<br>
-#define smu_set_ppfeature_status(smu, ppfeatures) \<br>
-       ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)<br>
-#define smu_get_ppfeature_status(smu, buf) \<br>
-       ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)<br>
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \<br>
         ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)<br>
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \<br>
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)<br>
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);<br>
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);<br>
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);<br>
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);<br>
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);<br>
 <br>
 #endif<br>
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
index c873228bf05f..cd0920093a5e 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c<br>
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_<br>
         return 0;<br>
 }<br>
 <br>
-static int navi10_get_ppfeature_status(struct smu_context *smu,<br>
-                                      char *buf)<br>
-{<br>
-       static const char *ppfeature_name[] = {<br>
-                               "DPM_PREFETCHER",<br>
-                               "DPM_GFXCLK",<br>
-                               "DPM_GFX_PACE",<br>
-                               "DPM_UCLK",<br>
-                               "DPM_SOCCLK",<br>
-                               "DPM_MP0CLK",<br>
-                               "DPM_LINK",<br>
-                               "DPM_DCEFCLK",<br>
-                               "MEM_VDDCI_SCALING",<br>
-                               "MEM_MVDD_SCALING",<br>
-                               "DS_GFXCLK",<br>
-                               "DS_SOCCLK",<br>
-                               "DS_LCLK",<br>
-                               "DS_DCEFCLK",<br>
-                               "DS_UCLK",<br>
-                               "GFX_ULV",<br>
-                               "FW_DSTATE",<br>
-                               "GFXOFF",<br>
-                               "BACO",<br>
-                               "VCN_PG",<br>
-                               "JPEG_PG",<br>
-                               "USB_PG",<br>
-                               "RSMU_SMN_CG",<br>
-                               "PPT",<br>
-                               "TDC",<br>
-                               "GFX_EDC",<br>
-                               "APCC_PLUS",<br>
-                               "GTHR",<br>
-                               "ACDC",<br>
-                               "VR0HOT",<br>
-                               "VR1HOT",<br>
-                               "FW_CTF",<br>
-                               "FAN_CONTROL",<br>
-                               "THERMAL",<br>
-                               "GFX_DCS",<br>
-                               "RM",<br>
-                               "LED_DISPLAY",<br>
-                               "GFX_SS",<br>
-                               "OUT_OF_BAND_MONITOR",<br>
-                               "TEMP_DEPENDENT_VMIN",<br>
-                               "MMHUB_PG",<br>
-                               "ATHUB_PG"};<br>
-       static const char *output_title[] = {<br>
-                               "FEATURES",<br>
-                               "BITMASK",<br>
-                               "ENABLEMENT"};<br>
-       uint64_t features_enabled;<br>
-       uint32_t feature_mask[2];<br>
-       int i;<br>
-       int ret = 0;<br>
-       int size = 0;<br>
-<br>
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
-       PP_ASSERT_WITH_CODE(!ret,<br>
-                       "[GetPPfeatureStatus] Failed to get enabled smc features!",<br>
-                       return ret);<br>
-       features_enabled = (uint64_t)feature_mask[0] |<br>
-                          (uint64_t)feature_mask[1] << 32;<br>
-<br>
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);<br>
-       size += sprintf(buf + size, "%-19s %-22s %s\n",<br>
-                               output_title[0],<br>
-                               output_title[1],<br>
-                               output_title[2]);<br>
-       for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {<br>
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",<br>
-                                       ppfeature_name[i],<br>
-                                       1ULL << i,<br>
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");<br>
-       }<br>
-<br>
-       return size;<br>
-}<br>
-<br>
-static int navi10_enable_smc_features(struct smu_context *smu,<br>
-                                     bool enabled,<br>
-                                     uint64_t feature_masks)<br>
-{<br>
-       struct smu_feature *feature = &smu->smu_feature;<br>
-       uint32_t feature_low, feature_high;<br>
-       uint32_t feature_mask[2];<br>
-       int ret = 0;<br>
-<br>
-       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);<br>
-       feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);<br>
-<br>
-       if (enabled) {<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,<br>
-                                                 feature_low);<br>
-               if (ret)<br>
-                       return ret;<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,<br>
-                                                 feature_high);<br>
-               if (ret)<br>
-                       return ret;<br>
-       } else {<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,<br>
-                                                 feature_low);<br>
-               if (ret)<br>
-                       return ret;<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,<br>
-                                                 feature_high);<br>
-               if (ret)<br>
-                       return ret;<br>
-       }<br>
-<br>
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
-       if (ret)<br>
-               return ret;<br>
-<br>
-       mutex_lock(&feature->mutex);<br>
-       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,<br>
-                   feature->feature_num);<br>
-       mutex_unlock(&feature->mutex);<br>
-<br>
-       return 0;<br>
-}<br>
-<br>
-static int navi10_set_ppfeature_status(struct smu_context *smu,<br>
-                                      uint64_t new_ppfeature_masks)<br>
-{<br>
-       uint64_t features_enabled;<br>
-       uint32_t feature_mask[2];<br>
-       uint64_t features_to_enable;<br>
-       uint64_t features_to_disable;<br>
-       int ret = 0;<br>
-<br>
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
-       PP_ASSERT_WITH_CODE(!ret,<br>
-                       "[SetPPfeatureStatus] Failed to get enabled smc features!",<br>
-                       return ret);<br>
-       features_enabled = (uint64_t)feature_mask[0] |<br>
-                          (uint64_t)feature_mask[1] << 32;<br>
-<br>
-       features_to_disable =<br>
-               features_enabled & ~new_ppfeature_masks;<br>
-       features_to_enable =<br>
-               ~features_enabled & new_ppfeature_masks;<br>
-<br>
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);<br>
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);<br>
-<br>
-       if (features_to_disable) {<br>
-               ret = navi10_enable_smc_features(smu, false, features_to_disable);<br>
-               PP_ASSERT_WITH_CODE(!ret,<br>
-                               "[SetPPfeatureStatus] Failed to disable smc features!",<br>
-                               return ret);<br>
-       }<br>
-<br>
-       if (features_to_enable) {<br>
-               ret = navi10_enable_smc_features(smu, true, features_to_enable);<br>
-               PP_ASSERT_WITH_CODE(!ret,<br>
-                               "[SetPPfeatureStatus] Failed to enable smc features!",<br>
-                               return ret);<br>
-       }<br>
-<br>
-       return 0;<br>
-}<br>
-<br>
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)<br>
 {<br>
         struct amdgpu_device *adev = smu->adev;<br>
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {<br>
         .set_watermarks_table = navi10_set_watermarks_table,<br>
         .read_sensor = navi10_read_sensor,<br>
         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,<br>
-       .get_ppfeature_status = navi10_get_ppfeature_status,<br>
-       .set_ppfeature_status = navi10_set_ppfeature_status,<br>
         .set_performance_level = navi10_set_performance_level,<br>
         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,<br>
 };<br>
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c<br>
index c06a9472c3b2..52c8fc9f1ff4 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c<br>
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)<br>
         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);<br>
 }<br>
 <br>
-static int vega20_get_enabled_smc_features(struct smu_context *smu,<br>
-               uint64_t *features_enabled)<br>
-{<br>
-       uint32_t feature_mask[2] = {0, 0};<br>
-       int ret = 0;<br>
-<br>
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);<br>
-       if (ret)<br>
-               return ret;<br>
-<br>
-       *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |<br>
-                       (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));<br>
-<br>
-       return ret;<br>
-}<br>
-<br>
-static int vega20_enable_smc_features(struct smu_context *smu,<br>
-               bool enable, uint64_t feature_mask)<br>
-{<br>
-       uint32_t smu_features_low, smu_features_high;<br>
-       int ret = 0;<br>
-<br>
-       smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);<br>
-       smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);<br>
-<br>
-       if (enable) {<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,<br>
-                                                 smu_features_low);<br>
-               if (ret)<br>
-                       return ret;<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,<br>
-                                                 smu_features_high);<br>
-               if (ret)<br>
-                       return ret;<br>
-       } else {<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,<br>
-                                                 smu_features_low);<br>
-               if (ret)<br>
-                       return ret;<br>
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,<br>
-                                                 smu_features_high);<br>
-               if (ret)<br>
-                       return ret;<br>
-       }<br>
-<br>
-       return 0;<br>
-<br>
-}<br>
-<br>
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)<br>
-{<br>
-       static const char *ppfeature_name[] = {<br>
-                               "DPM_PREFETCHER",<br>
-                               "GFXCLK_DPM",<br>
-                               "UCLK_DPM",<br>
-                               "SOCCLK_DPM",<br>
-                               "UVD_DPM",<br>
-                               "VCE_DPM",<br>
-                               "ULV",<br>
-                               "MP0CLK_DPM",<br>
-                               "LINK_DPM",<br>
-                               "DCEFCLK_DPM",<br>
-                               "GFXCLK_DS",<br>
-                               "SOCCLK_DS",<br>
-                               "LCLK_DS",<br>
-                               "PPT",<br>
-                               "TDC",<br>
-                               "THERMAL",<br>
-                               "GFX_PER_CU_CG",<br>
-                               "RM",<br>
-                               "DCEFCLK_DS",<br>
-                               "ACDC",<br>
-                               "VR0HOT",<br>
-                               "VR1HOT",<br>
-                               "FW_CTF",<br>
-                               "LED_DISPLAY",<br>
-                               "FAN_CONTROL",<br>
-                               "GFX_EDC",<br>
-                               "GFXOFF",<br>
-                               "CG",<br>
-                               "FCLK_DPM",<br>
-                               "FCLK_DS",<br>
-                               "MP1CLK_DS",<br>
-                               "MP0CLK_DS",<br>
-                               "XGMI",<br>
-                               "ECC"};<br>
-       static const char *output_title[] = {<br>
-                               "FEATURES",<br>
-                               "BITMASK",<br>
-                               "ENABLEMENT"};<br>
-       uint64_t features_enabled;<br>
-       int i;<br>
-       int ret = 0;<br>
-       int size = 0;<br>
-<br>
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);<br>
-       if (ret)<br>
-               return ret;<br>
-<br>
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);<br>
-       size += sprintf(buf + size, "%-19s %-22s %s\n",<br>
-                               output_title[0],<br>
-                               output_title[1],<br>
-                               output_title[2]);<br>
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {<br>
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",<br>
-                                       ppfeature_name[i],<br>
-                                       1ULL << i,<br>
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");<br>
-       }<br>
-<br>
-       return size;<br>
-}<br>
-<br>
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)<br>
-{<br>
-       uint64_t features_enabled;<br>
-       uint64_t features_to_enable;<br>
-       uint64_t features_to_disable;<br>
-       int ret = 0;<br>
-<br>
-       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))<br>
-               return -EINVAL;<br>
-<br>
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);<br>
-       if (ret)<br>
-               return ret;<br>
-<br>
-       features_to_disable =<br>
-               features_enabled & ~new_ppfeature_masks;<br>
-       features_to_enable =<br>
-               ~features_enabled & new_ppfeature_masks;<br>
-<br>
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);<br>
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);<br>
-<br>
-       if (features_to_disable) {<br>
-               ret = vega20_enable_smc_features(smu, false, features_to_disable);<br>
-               if (ret)<br>
-                       return ret;<br>
-       }<br>
-<br>
-       if (features_to_enable) {<br>
-               ret = vega20_enable_smc_features(smu, true, features_to_enable);<br>
-               if (ret)<br>
-                       return ret;<br>
-       }<br>
-<br>
-       return 0;<br>
-}<br>
-<br>
 static bool vega20_is_dpm_running(struct smu_context *smu)<br>
 {<br>
         int ret = 0;<br>
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {<br>
         .force_dpm_limit_value = vega20_force_dpm_limit_value,<br>
         .unforce_dpm_levels = vega20_unforce_dpm_levels,<br>
         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,<br>
-       .set_ppfeature_status = vega20_set_ppfeature_status,<br>
-       .get_ppfeature_status = vega20_get_ppfeature_status,<br>
         .is_dpm_running = vega20_is_dpm_running,<br>
         .set_thermal_fan_table = vega20_set_thermal_fan_table,<br>
         .get_fan_speed_percent = vega20_get_fan_speed_percent,<br>
-- <br>
2.22.0</p>
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