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Please include a patch description. <br>
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<br>
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Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tao Zhou <tao.zhou1@amd.com><br>
<b>Sent:</b> Thursday, August 1, 2019 2:43 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>; Li, Dennis <Dennis.Li@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Pan, Xinhui <Xinhui.Pan@amd.com><br>
<b>Cc:</b> Zhou1, Tao <Tao.Zhou1@amd.com><br>
<b>Subject:</b> [PATCH 3/6] drm/amdgpu: initialize new parameters and functions for amdgpu_umc structure</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Signed-off-by: Tao Zhou <tao.zhou1@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++++--<br>
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++++++-<br>
drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 3 +++<br>
3 files changed, 17 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
index ee06cbe2a7e7..3486b4ce7770 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
@@ -631,8 +631,11 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)<br>
{<br>
switch (adev->asic_type) {<br>
case CHIP_VEGA20:<br>
- adev->umc.max_ras_err_cnt_per_query =<br>
- UMC_V6_1_UMC_INSTANCE_NUM * UMC_V6_1_CHANNEL_INSTANCE_NUM;<br>
+ adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;<br>
+ adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;<br>
+ adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;<br>
+ adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;<br>
+ adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];<br>
adev->umc.funcs = &umc_v6_1_funcs;<br>
break;<br>
default:<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c<br>
index 035e4fea472c..9ba015d7eb57 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c<br>
@@ -41,7 +41,7 @@<br>
/* offset in 256B block */<br>
#define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL)<br>
<br>
-static uint32_t<br>
+const uint32_t<br>
umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {<br>
{2, 18, 11, 27}, {4, 20, 13, 29},<br>
{1, 17, 8, 24}, {7, 23, 14, 30},<br>
@@ -235,7 +235,15 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,<br>
umc_v6_1_disable_umc_index_mode(adev);<br>
}<br>
<br>
+static void umc_v6_1_ras_init(struct amdgpu_device *adev)<br>
+{<br>
+<br>
+}<br>
+<br>
const struct amdgpu_umc_funcs umc_v6_1_funcs = {<br>
+ .ras_init = umc_v6_1_ras_init,<br>
.query_ras_error_count = umc_v6_1_query_ras_error_count,<br>
.query_ras_error_address = umc_v6_1_query_ras_error_address,<br>
+ .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,<br>
+ .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode,<br>
};<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h<br>
index bddaf14a77f9..ad4598c0e495 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h<br>
@@ -24,6 +24,7 @@<br>
#define __UMC_V6_1_H__<br>
<br>
#include "soc15_common.h"<br>
+#include "amdgpu.h"<br>
<br>
/* HBM Memory Channel Width */<br>
#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128<br>
@@ -37,5 +38,7 @@<br>
#define UMC_V6_1_PER_CHANNEL_OFFSET 0x800<br>
<br>
extern const struct amdgpu_umc_funcs umc_v6_1_funcs;<br>
+extern const uint32_t<br>
+ umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];<br>
<br>
#endif<br>
-- <br>
2.17.1<br>
<br>
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