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Please include a patch description. Explain why you need the new interface.</div>
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Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tao Zhou <tao.zhou1@amd.com><br>
<b>Sent:</b> Thursday, August 1, 2019 2:43 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>; Li, Dennis <Dennis.Li@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Pan, Xinhui <Xinhui.Pan@amd.com><br>
<b>Cc:</b> Zhou1, Tao <Tao.Zhou1@amd.com><br>
<b>Subject:</b> [PATCH 2/6] drm/amdgpu: add more parameters and functions to amdgpu_umc structure</font>
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<div class="PlainText">Signed-off-by: Tao Zhou <tao.zhou1@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 13 +++++++++++++<br>
drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 2 ++<br>
2 files changed, 15 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h<br>
index dfa1a39e57af..2604f5076867 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h<br>
@@ -22,15 +22,28 @@<br>
#define __AMDGPU_UMC_H__<br>
<br>
struct amdgpu_umc_funcs {<br>
+ void (*ras_init)(struct amdgpu_device *adev);<br>
void (*query_ras_error_count)(struct amdgpu_device *adev,<br>
void *ras_error_status);<br>
void (*query_ras_error_address)(struct amdgpu_device *adev,<br>
void *ras_error_status);<br>
+ void (*enable_umc_index_mode)(struct amdgpu_device *adev,<br>
+ uint32_t umc_instance);<br>
+ void (*disable_umc_index_mode)(struct amdgpu_device *adev);<br>
};<br>
<br>
struct amdgpu_umc {<br>
/* max error count in one ras query call */<br>
uint32_t max_ras_err_cnt_per_query;<br>
+ /* number of umc channel instance with memory map register access */<br>
+ uint32_t channel_inst_num;<br>
+ /* number of umc instance with memory map register access */<br>
+ uint32_t umc_inst_num;<br>
+ /* UMC regiser per channel offset */<br>
+ uint32_t channel_offs;<br>
+ /* channel index table of interleaved memory */<br>
+ const uint32_t *channel_idx_tbl;<br>
+<br>
const struct amdgpu_umc_funcs *funcs;<br>
};<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h<br>
index d25ae414f4d8..bddaf14a77f9 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h<br>
@@ -31,6 +31,8 @@<br>
#define UMC_V6_1_CHANNEL_INSTANCE_NUM 4<br>
/* number of umc instance with memory map register access */<br>
#define UMC_V6_1_UMC_INSTANCE_NUM 8<br>
+/* total channel instances in one umc block */<br>
+#define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)<br>
/* UMC regiser per channel offset */<br>
#define UMC_V6_1_PER_CHANNEL_OFFSET 0x800<br>
<br>
-- <br>
2.17.1<br>
<br>
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