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Please include a patch description. Explain why you need the new helper function.</div>
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Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tao Zhou <tao.zhou1@amd.com><br>
<b>Sent:</b> Thursday, August 1, 2019 2:43 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>; Li, Dennis <Dennis.Li@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Pan, Xinhui <Xinhui.Pan@amd.com><br>
<b>Cc:</b> Zhou1, Tao <Tao.Zhou1@amd.com><br>
<b>Subject:</b> [PATCH 4/6] drm/amdgpu: add macro of umc for each channel</font>
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<div class="PlainText">common function for all umc versions<br>
<br>
Signed-off-by: Tao Zhou <tao.zhou1@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 23 +++++++++++++++++++++++<br>
1 file changed, 23 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h<br>
index 2604f5076867..9efdd66279e5 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h<br>
@@ -21,6 +21,29 @@<br>
#ifndef __AMDGPU_UMC_H__<br>
#define __AMDGPU_UMC_H__<br>
<br>
+/*<br>
+ * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,<br>
+ * uint32_t umc_reg_offset, uint32_t channel_index)<br>
+ */<br>
+#define amdgpu_umc_for_each_channel(func) \<br>
+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; \<br>
+ uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \<br>
+ for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) { \<br>
+ /* enable the index mode to query eror count per channel */ \<br>
+ adev->umc.funcs->enable_umc_index_mode(adev, umc_inst); \<br>
+ for (channel_inst = 0; \<br>
+ channel_inst < adev->umc.channel_inst_num; \<br>
+ channel_inst++) { \<br>
+ /* calc the register offset according to channel instance */ \<br>
+ umc_reg_offset = adev->umc.channel_offs * channel_inst; \<br>
+ /* get channel index of interleaved memory */ \<br>
+ channel_index = adev->umc.channel_idx_tbl[ \<br>
+ umc_inst * adev->umc.channel_inst_num + channel_inst]; \<br>
+ (func)(adev, err_data, umc_reg_offset, channel_index); \<br>
+ } \<br>
+ } \<br>
+ adev->umc.funcs->disable_umc_index_mode(adev);<br>
+<br>
struct amdgpu_umc_funcs {<br>
void (*ras_init)(struct amdgpu_device *adev);<br>
void (*query_ras_error_count)(struct amdgpu_device *adev,<br>
-- <br>
2.17.1<br>
<br>
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