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Series is:</div>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Yuan, Xiaojie <Xiaojie.Yuan@amd.com><br>
<b>Sent:</b> Thursday, August 15, 2019 5:48 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Xiao, Jack <Jack.Xiao@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com><br>
<b>Subject:</b> [PATCH 2/2] drm/amdgpu: add firmware header printing for psp fw loading</font>
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<div class="PlainText">firmware header information is printed for direct fw loading but not<br>
added for psp fw loading yet<br>
<br>
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 54 +++++++++++++++++++++++++<br>
1 file changed, 54 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
index 4b2d2fd72dc6..7715c0da5229 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
@@ -944,6 +944,58 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,<br>
return 0;<br>
}<br>
<br>
+static void psp_print_fw_hdr(struct psp_context *psp,<br>
+ struct amdgpu_firmware_info *ucode)<br>
+{<br>
+ struct amdgpu_device *adev = psp->adev;<br>
+ const struct sdma_firmware_header_v1_0 *sdma_hdr =<br>
+ (const struct sdma_firmware_header_v1_0 *)<br>
+ adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;<br>
+ const struct gfx_firmware_header_v1_0 *ce_hdr =<br>
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;<br>
+ const struct gfx_firmware_header_v1_0 *pfp_hdr =<br>
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;<br>
+ const struct gfx_firmware_header_v1_0 *me_hdr =<br>
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;<br>
+ const struct gfx_firmware_header_v1_0 *mec_hdr =<br>
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;<br>
+ const struct rlc_firmware_header_v2_0 *rlc_hdr =<br>
+ (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;<br>
+ const struct smc_firmware_header_v1_0 *smc_hdr =<br>
+ (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;<br>
+<br>
+ switch (ucode->ucode_id) {<br>
+ case AMDGPU_UCODE_ID_SDMA0:<br>
+ case AMDGPU_UCODE_ID_SDMA1:<br>
+ case AMDGPU_UCODE_ID_SDMA2:<br>
+ case AMDGPU_UCODE_ID_SDMA3:<br>
+ case AMDGPU_UCODE_ID_SDMA4:<br>
+ case AMDGPU_UCODE_ID_SDMA5:<br>
+ case AMDGPU_UCODE_ID_SDMA6:<br>
+ case AMDGPU_UCODE_ID_SDMA7:<br>
+ amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);<br>
+ break;<br>
+ case AMDGPU_UCODE_ID_CP_CE:<br>
+ amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);<br>
+ break;<br>
+ case AMDGPU_UCODE_ID_CP_PFP:<br>
+ amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);<br>
+ break;<br>
+ case AMDGPU_UCODE_ID_CP_ME:<br>
+ amdgpu_ucode_print_gfx_hdr(&me_hdr->header);<br>
+ break;<br>
+ case AMDGPU_UCODE_ID_CP_MEC1:<br>
+ amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);<br>
+ break;<br>
+ case AMDGPU_UCODE_ID_RLC_G:<br>
+ amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);<br>
+ break;<br>
+ case AMDGPU_UCODE_ID_SMC:<br>
+ amdgpu_ucode_print_smc_hdr(&smc_hdr->header);<br>
+ break;<br>
+ }<br>
+}<br>
+<br>
static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,<br>
struct psp_gfx_cmd_resp *cmd)<br>
{<br>
@@ -1028,6 +1080,8 @@ static int psp_np_fw_load(struct psp_context *psp)<br>
ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)<br>
continue;<br>
<br>
+ psp_print_fw_hdr(psp, ucode);<br>
+<br>
ret = psp_execute_np_fw_load(psp, ucode);<br>
if (ret)<br>
return ret;<br>
-- <br>
2.20.1<br>
<br>
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