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<p>sure, i know, I feel this is not a good way to do code when other asics have similar problems.<br>
we'd better add a helper function to check which sysfs interface is supported for each asic.<br>
or move these sysfs interface to asic file to create.<br>
</p>
<p>anyway, we can optimize this logic later.<br>
Reviewed-by: Kevin Wang <a class="moz-txt-link-rfc2396E" href="mailto:kevin1.wang@amd.com">
<kevin1.wang@amd.com></a><br>
<br>
Best Regards,<br>
Kevin<br>
</p>
<div class="moz-cite-prefix">On 8/16/19 3:52 PM, Quan, Evan wrote:<br>
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<p class="MsoNormal">Bascially, we should not expose the sysfs interface for those features not supported by the ASIC.<o:p></o:p></p>
<p class="MsoNormal">As, there are some tools/tests which judges whether the feature is supported by the existence of the file.<o:p></o:p></p>
<p class="MsoNormal">This can fix some test failure in rocm test suit.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Evan<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> Wang, Kevin(Yang) <a class="moz-txt-link-rfc2396E" href="mailto:Kevin1.Wang@amd.com">
<Kevin1.Wang@amd.com></a> <br>
<b>Sent:</b> Friday, August 16, 2019 3:16 PM<br>
<b>To:</b> Quan, Evan <a class="moz-txt-link-rfc2396E" href="mailto:Evan.Quan@amd.com">
<Evan.Quan@amd.com></a>; <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">
amd-gfx@lists.freedesktop.org</a><br>
<b>Subject:</b> Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">I don't recommend it. What's the problem if we keep it the way it is?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">maybe other asic also has same problems, if do it, the other asic should add a condition in there too.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">eg: navi10 don't support sensor of "pp_dpm_pcie".<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Best Regards,<br>
Kevin<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org" moz-do-not-send="true">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of Evan Quan <<a href="mailto:evan.quan@amd.com" moz-do-not-send="true">evan.quan@amd.com</a>><br>
<b>Sent:</b> Friday, August 16, 2019 2:08 PM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">
amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a>><br>
<b>Cc:</b> Quan, Evan <<a href="mailto:Evan.Quan@amd.com" moz-do-not-send="true">Evan.Quan@amd.com</a>><br>
<b>Subject:</b> [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs</span>
<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Do not expose those unsupported clock domains through sysfs on<br>
Arcturus.<br>
<br>
Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844<br>
Signed-off-by: Evan Quan <<a href="mailto:evan.quan@amd.com" moz-do-not-send="true">evan.quan@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 ++++++++++++++++----------<br>
1 file changed, 16 insertions(+), 10 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
index c5642be9b44b..7accf2c7f8cd 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)<br>
DRM_ERROR("failed to create device file pp_dpm_socclk\n");<br>
return ret;<br>
}<br>
- ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
- if (ret) {<br>
- DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");<br>
- return ret;<br>
+ if (adev->asic_type != CHIP_ARCTURUS) {<br>
+ ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
+ if (ret) {<br>
+ DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");<br>
+ return ret;<br>
+ }<br>
}<br>
}<br>
if (adev->asic_type >= CHIP_VEGA20) {<br>
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)<br>
return ret;<br>
}<br>
}<br>
- ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
- if (ret) {<br>
- DRM_ERROR("failed to create device file pp_dpm_pcie\n");<br>
- return ret;<br>
+ if (adev->asic_type != CHIP_ARCTURUS) {<br>
+ ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
+ if (ret) {<br>
+ DRM_ERROR("failed to create device file pp_dpm_pcie\n");<br>
+ return ret;<br>
+ }<br>
}<br>
ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);<br>
if (ret) {<br>
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);<br>
if (adev->asic_type >= CHIP_VEGA10) {<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);<br>
- device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
+ if (adev->asic_type != CHIP_ARCTURUS)<br>
+ device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
}<br>
- device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
+ if (adev->asic_type != CHIP_ARCTURUS)<br>
+ device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
if (adev->asic_type >= CHIP_VEGA20)<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);<br>
device_remove_file(adev->dev, &dev_attr_pp_sclk_od);<br>
-- <br>
2.22.0<br>
<br>
_______________________________________________<br>
amd-gfx mailing list<br>
<a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a><br>
<a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" moz-do-not-send="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><o:p></o:p></p>
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