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<span>I don't recommend it. What's the problem if we keep it the way it is?</span></div>
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<span>maybe other asic also has same problems, if do it, the other asic should add a condition in there too.</span></div>
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<span>eg: navi10 don't support sensor of "pp_dpm_pcie".</span></div>
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<span></span></div>
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Best Regards,<br>
Kevin</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Friday, August 16, 2019 2:08 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Do not expose those unsupported clock domains through sysfs on<br>
Arcturus.<br>
<br>
Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 ++++++++++++++++----------<br>
1 file changed, 16 insertions(+), 10 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
index c5642be9b44b..7accf2c7f8cd 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)<br>
DRM_ERROR("failed to create device file pp_dpm_socclk\n");<br>
return ret;<br>
}<br>
- ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
- if (ret) {<br>
- DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");<br>
- return ret;<br>
+ if (adev->asic_type != CHIP_ARCTURUS) {<br>
+ ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
+ if (ret) {<br>
+ DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");<br>
+ return ret;<br>
+ }<br>
}<br>
}<br>
if (adev->asic_type >= CHIP_VEGA20) {<br>
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)<br>
return ret;<br>
}<br>
}<br>
- ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
- if (ret) {<br>
- DRM_ERROR("failed to create device file pp_dpm_pcie\n");<br>
- return ret;<br>
+ if (adev->asic_type != CHIP_ARCTURUS) {<br>
+ ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
+ if (ret) {<br>
+ DRM_ERROR("failed to create device file pp_dpm_pcie\n");<br>
+ return ret;<br>
+ }<br>
}<br>
ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);<br>
if (ret) {<br>
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);<br>
if (adev->asic_type >= CHIP_VEGA10) {<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);<br>
- device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
+ if (adev->asic_type != CHIP_ARCTURUS)<br>
+ device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);<br>
}<br>
- device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
+ if (adev->asic_type != CHIP_ARCTURUS)<br>
+ device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
if (adev->asic_type >= CHIP_VEGA20)<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);<br>
device_remove_file(adev->dev, &dev_attr_pp_sclk_od);<br>
-- <br>
2.22.0<br>
<br>
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