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Hi Christian,</div>
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Thank you very much for your suggestions!</div>
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A little more improvement have made about the patch1, please review again.</div>
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BTW, any suggestion about the patch2?</div>
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Rico<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Christian König <ckoenig.leichtzumerken@gmail.com><br>
<b>Sent:</b> Wednesday, August 28, 2019 21:09<br>
<b>To:</b> Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Xu, Feifei <Feifei.Xu@amd.com>; Ma, Le <Le.Ma@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com><br>
<b>Subject:</b> Re: [PATCH 1/2] drm/amdgpu/psp: keep TMR in visible vram region for SRIOV</font>
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<div class="PlainText">Am 28.08.19 um 13:40 schrieb Tianci Yin:<br>
> From: "Tianci.Yin" <tianci.yin@amd.com><br>
><br>
> Fix compute ring test failure in sriov scenario.<br>
><br>
> Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3<br>
> Signed-off-by: Tianci.Yin <tianci.yin@amd.com><br>
<br>
Reviewed-by: Christian König <christian.koenig@amd.com> for both patches.<br>
<br>
> ---<br>
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +++++++++++----<br>
> 1 file changed, 11 insertions(+), 4 deletions(-)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
> index 9f7cc5b..43fa8b7 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
> @@ -239,6 +239,7 @@ static int psp_tmr_init(struct psp_context *psp)<br>
> {<br>
> int ret;<br>
> int tmr_size;<br>
> + void *tmr_buf;<br>
> <br>
> /*<br>
> * According to HW engineer, they prefer the TMR address be "naturally<br>
> @@ -261,9 +262,14 @@ static int psp_tmr_init(struct psp_context *psp)<br>
> }<br>
> }<br>
> <br>
> - ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,<br>
> - AMDGPU_GEM_DOMAIN_VRAM,<br>
> - &psp->tmr_bo, &psp->tmr_mc_addr, NULL);<br>
> + if (!amdgpu_sriov_vf(psp->adev))<br>
> + ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,<br>
> + AMDGPU_GEM_DOMAIN_VRAM,<br>
> + &psp->tmr_bo, &psp->tmr_mc_addr, NULL);<br>
> + else<br>
> + ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,<br>
> + AMDGPU_GEM_DOMAIN_VRAM,<br>
> + &psp->tmr_bo, &psp->tmr_mc_addr, &tmr_buf);<br>
> <br>
> return ret;<br>
> }<br>
> @@ -1206,6 +1212,7 @@ static int psp_hw_fini(void *handle)<br>
> {<br>
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
> struct psp_context *psp = &adev->psp;<br>
> + void *tmr_buf;<br>
> <br>
> if (adev->gmc.xgmi.num_physical_nodes > 1 &&<br>
> psp->xgmi_context.initialized == 1)<br>
> @@ -1216,7 +1223,7 @@ static int psp_hw_fini(void *handle)<br>
> <br>
> psp_ring_destroy(psp, PSP_RING_TYPE__KM);<br>
> <br>
> - amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, NULL);<br>
> + amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &tmr_buf);<br>
> amdgpu_bo_free_kernel(&psp->fw_pri_bo,<br>
> &psp->fw_pri_mc_addr, &psp->fw_pri_buf);<br>
> amdgpu_bo_free_kernel(&psp->fence_buf_bo,<br>
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