<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="blue" vlink="purple"> <div class="WordSection1"> <p class="MsoNormal">That’s a good point for simplifying the code and will send another patch for this.<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Thanks,<o:p></o:p></p> <p class="MsoNormal">Prike<o:p></o:p></p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> <p class="MsoNormal"><b>From:</b> Wang, Kevin(Yang) <Kevin1.Wang@amd.com> <br> <b>Sent:</b> Monday, September 23, 2019 5:22 PM<br> <b>To:</b> Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> arron.liu@amd.com; Huang, Ray <Ray.Huang@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com><br> <b>Subject:</b> Re: [PATCH 1/5] drm/amd/powerplay: bypass dpm_context null pointer check guard for some smu series<o:p></o:p></p> </div> </div> <p class="MsoNormal"><o:p> </o:p></p> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">the smu driver many place will use AMD_IS_APU flags,<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">i think we'd better add a new member "is_apu" in smu_context"<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Best Regards,<br> kevin<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> <p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of Liang, Prike <<a href="mailto:Prike.Liang@amd.com">Prike.Liang@amd.com</a>><br> <b>Sent:</b> Monday, September 23, 2019 4:43 PM<br> <b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br> <b>Cc:</b> <a href="mailto:arron.liu@amd.com">arron.liu@amd.com</a> <<a href="mailto:arron.liu@amd.com">arron.liu@amd.com</a>>; Huang, Ray <<a href="mailto:Ray.Huang@amd.com">Ray.Huang@amd.com</a>>; Liang, Prike <<a href="mailto:Prike.Liang@amd.com">Prike.Liang@amd.com</a>>; Quan, Evan <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>>; Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>><br> <b>Subject:</b> [PATCH 1/5] drm/amd/powerplay: bypass dpm_context null pointer check guard for some smu series</span> <o:p></o:p></p> <div> <p class="MsoNormal"> <o:p></o:p></p> </div> </div> <div> <div> <p class="MsoNormal">For now APU has no smu_dpm_context structure for containing default/current related dpm table,<br> thus will not initialize smu_dpm_context and aviod null pointer check guard for APU.<br> <br> Signed-off-by: Prike Liang <<a href="mailto:Prike.Liang@amd.com">Prike.Liang@amd.com</a>><br> ---<br> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 +++++++---<br> 1 file changed, 7 insertions(+), 3 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br> index 90fa444..3afd2cd 100644<br> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br> @@ -1554,7 +1554,9 @@ static int smu_enable_umd_pstate(void *handle,<br> <br> struct smu_context *smu = (struct smu_context*)(handle);<br> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);<br> - if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)<br> + struct amdgpu_device *adev = smu->adev;<br> +<br> + if (!(adev->flags & AMD_IS_APU) && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))<br> return -EINVAL;<br> <br> if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {<br> @@ -1751,8 +1753,9 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)<br> {<br> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);<br> enum amd_dpm_forced_level level;<br> + struct amdgpu_device *adev = smu->adev;<br> <br> - if (!smu_dpm_ctx->dpm_context)<br> + if (!(adev->flags & AMD_IS_APU) && !smu_dpm_ctx->dpm_context)<br> return -EINVAL;<br> <br> mutex_lock(&(smu->mutex));<br> @@ -1766,8 +1769,9 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev<br> {<br> struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);<br> int ret = 0;<br> + struct amdgpu_device *adev = smu->adev;<br> <br> - if (!smu_dpm_ctx->dpm_context)<br> + if (!(adev->flags & AMD_IS_APU) && !smu_dpm_ctx->dpm_context)<br> return -EINVAL;<br> <br> ret = smu_enable_umd_pstate(smu, &level);<br> -- <br> 2.7.4<br> <br> _______________________________________________<br> amd-gfx mailing list<br> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><o:p></o:p></p> </div> </div> </div> </div> </body> </html>