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this patch is not needed for apu.</div>
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by default, the smu will use max value as peak value.</div>
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refs:smu_default_set_performance_level</div>
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Best Regards,</div>
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Kevin</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Liang, Prike <Prike.Liang@amd.com><br>
<b>Sent:</b> Thursday, September 26, 2019 11:50 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Liang, Prike <Prike.Liang@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Huang, Ray <Ray.Huang@amd.com>; keneth.feng@amd.com <keneth.feng@amd.com><br>
<b>Subject:</b> [PATCH 7/8] drm/amd/powerplay: implement the interface for setting sclk/uclk profile_peak level</font>
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<div class="PlainText">Add the interface for setting sclk and uclk peak frequency.<br>
<br>
Signed-off-by: Prike Liang <Prike.Liang@amd.com><br>
---<br>
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 40 ++++++++++++++++++++++++++++++<br>
 1 file changed, 40 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c<br>
index 151d78e..c63518a 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c<br>
@@ -510,6 +510,45 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u<br>
         return 0;<br>
 }<br>
 <br>
+static int renoir_set_peak_clock_by_device(struct smu_context *smu)<br>
+{<br>
+       int ret = 0;<br>
+       uint32_t sclk_freq = 0, uclk_freq = 0;<br>
+<br>
+       ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);<br>
+       if (ret)<br>
+               return ret;<br>
+<br>
+       return ret;<br>
+}<br>
+<br>
+static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)<br>
+{<br>
+       int ret = 0;<br>
+<br>
+       switch (level) {<br>
+       case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:<br>
+               ret = renoir_set_peak_clock_by_device(smu);<br>
+               break;<br>
+       default:<br>
+               ret = -EINVAL;<br>
+               break;<br>
+       }<br>
+<br>
+       return ret;<br>
+}<br>
 <br>
 static const struct pptable_funcs renoir_ppt_funcs = {<br>
         .get_smu_msg_index = renoir_get_smu_msg_index,<br>
@@ -526,6 +565,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {<br>
         .get_profiling_clk_mask = renoir_get_profiling_clk_mask,<br>
         .force_clk_levels = renoir_force_clk_levels,<br>
         .set_power_profile_mode = renoir_set_power_profile_mode,<br>
+       .set_performance_level = renoir_set_performance_level,<br>
 };<br>
 <br>
 void renoir_set_ppt_funcs(struct smu_context *smu)<br>
-- <br>
2.7.4<br>
<br>
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