<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style> </head> <body dir="ltr"> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Not much relationship between them, except that this functional change is to fix a IOCTL error printing. </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Yong</div> <div id="appendonsend"></div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">From: Kuehling, Felix <Felix.Kuehling@amd.com> Sent: Monday, September 30, 2019 11:57 AM To: Zhao, Yong <Yong.Zhao@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org> Subject: Re: [PATCH 5/6] drm/amdgpu: Add the HDP flush support for Navi <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">As far as I can tell, this is the only patch with functional changes in the patch series. The rest are purely clean-up. Any relation I'm missing? Anyway, patches 2,3,5 are Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> On 2019-09-27 11:41 p.m., Zhao, Yong wrote: > The HDP flush support code was missing in the nbio and nv files. > > Change-Id: I046ff52567676b56bf16dc1728b02481233acb61 > Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 16 +++++++++++++--- > drivers/gpu/drm/amd/amdgpu/nv.c | 9 +++++++++ > 2 files changed, 22 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > index e7e36fb6113d..c699cbfe015a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c > @@ -27,11 +27,21 @@ > #include "nbio/nbio_2_3_default.h" > #include "nbio/nbio_2_3_offset.h" > #include "nbio/nbio_2_3_sh_mask.h" > +#include <uapi/linux/kfd_ioctl.h> > > #define smnPCIE_CONFIG_CNTL 0x11180044 > #define smnCPM_CONTROL 0x11180460 > #define smnPCIE_CNTL2 0x11180070 > > + > +static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev) > +{ > + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, > + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); > + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, > + adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); > +} > + > static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) > { > u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); > @@ -56,10 +66,9 @@ static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev, > struct amdgpu_ring *ring) > { > if (!ring || !ring->funcs->emit_wreg) > - WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); > + WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); > else > - amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( > - NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL), 0); > + amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); > } > > static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev) > @@ -330,4 +339,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { > .ih_control = nbio_v2_3_ih_control, > .init_registers = nbio_v2_3_init_registers, > .detect_hw_virt = nbio_v2_3_detect_hw_virt, > + .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, > }; > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c > index b3e7756fcc4b..6699a45b88ec 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nv.c > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c > @@ -587,8 +587,11 @@ static const struct amdgpu_asic_funcs nv_asic_funcs = > > static int nv_common_early_init(void *handle) > { > +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > > + adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; > + adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; > adev->smc_rreg = NULL; > adev->smc_wreg = NULL; > adev->pcie_rreg = &nv_pcie_rreg; > @@ -714,6 +717,12 @@ static int nv_common_hw_init(void *handle) > nv_program_aspm(adev); > /* setup nbio registers */ > adev->nbio.funcs->init_registers(adev); > + /* remap HDP registers to a hole in mmio space, > + * for the purpose of expose those registers > + * to process space > + */ > + if (adev->nbio.funcs->remap_hdp_registers) > + adev->nbio.funcs->remap_hdp_registers(adev); > /* enable the doorbell aperture */ > nv_enable_doorbell_aperture(adev, true); > </div> </div> </body> </html>