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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Jack Zhang <Jack.Zhang1@amd.com><br>
<b>Sent:</b> Monday, September 30, 2019 1:00 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhang, Jack (Jian) <Jack.Zhang1@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/amdgpu/sriov ip block setting of Arcturus</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt">
<div class="PlainText">Add ip block setting for Arcturus SRIOV<br>
<br>
1.PSP need to be initialized before IH.<br>
2.SMU doesn't need to be initialized at kmd driver.<br>
3.Arcturus doesn't support DCE hardware,it needs to skip<br>
register access to DCE.<br>
<br>
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++++++----<br>
drivers/gpu/drm/amd/amdgpu/soc15.c | 19 +++++++++++++++----<br>
2 files changed, 21 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
index 95a9a5f5..44023bd 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
@@ -1330,11 +1330,13 @@ static int gmc_v9_0_hw_init(void *handle)<br>
gmc_v9_0_init_golden_registers(adev);<br>
<br>
if (adev->mode_info.num_crtc) {<br>
- /* Lockout access through VGA aperture*/<br>
- WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);<br>
+ if (adev->asic_type != CHIP_ARCTURUS) {<br>
+ /* Lockout access through VGA aperture*/<br>
+ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);<br>
<br>
- /* disable VGA render */<br>
- WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);<br>
+ /* disable VGA render */<br>
+ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);<br>
+ }<br>
}<br>
<br>
</div>
<div class="PlainText"><span style="color: rgb(111, 192, 64);">This is a general bug fix and should be split out into a separate patch.</span></div>
<div class="PlainText"><br>
</div>
<div class="PlainText"><span style="color: rgb(111, 192, 64);">Alex</span><br>
</div>
<div class="PlainText"><br>
</div>
<div class="PlainText"> r = gmc_v9_0_gart_enable(adev);<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c<br>
index dbd790e..ac181e3 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c<br>
@@ -754,14 +754,25 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)<br>
case CHIP_ARCTURUS:<br>
amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);<br>
amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);<br>
- amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);<br>
- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))<br>
- amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);<br>
+<br>
+ /* For MI100 SR-IOV, PSP need to be initialized before IH */<br>
+ if (amdgpu_sriov_vf(adev)) {<br>
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))<br>
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);<br>
+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);<br>
+ } else {<br>
+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);<br>
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))<br>
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);<br>
+ }<br>
+<br>
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))<br>
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);<br>
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);<br>
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);<br>
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);<br>
+ if (!amdgpu_sriov_vf(adev))<br>
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);<br>
+<br>
if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))<br>
amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);<br>
break;<br>
-- <br>
2.7.4<br>
<br>
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