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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Zhao, Yong <Yong.Zhao@amd.com><br>
<b>Sent:</b> Friday, September 27, 2019 11:40 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhao, Yong <Yong.Zhao@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Export setup_vm_pt_regs() logic for mmhub 2.0</font>
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<div class="PlainText">The KFD code will call this function later.<br>
<br>
Change-Id: I5993323603799963e9eb473852b6c72de2172ed6<br>
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 19 ++++++++++++-------<br>
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h |  2 ++<br>
 2 files changed, 14 insertions(+), 7 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c<br>
index 86ed8cb915a8..2eea702de8ee 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c<br>
@@ -31,20 +31,25 @@<br>
 <br>
 #include "soc15_common.h"<br>
 <br>
-static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)<br>
+void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
+                               uint64_t page_table_base)<br>
 {<br>
-       uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);<br>
+       /* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */<br>
+       int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32<br>
+                       - mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;<br>
 <br>
-       WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,<br>
-                    lower_32_bits(value));<br>
+       WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,<br>
+                       offset * vmid, lower_32_bits(page_table_base));<br>
 <br>
-       WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,<br>
-                    upper_32_bits(value));<br>
+       WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,<br>
+                       offset * vmid, upper_32_bits(page_table_base));<br>
 }<br>
 <br>
 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)<br>
 {<br>
-       mmhub_v2_0_init_gart_pt_regs(adev);<br>
+       uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);<br>
+<br>
+       mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);<br>
 <br>
         WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,<br>
                      (u32)(adev->gmc.gart_start >> 12));<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h<br>
index db16f3ece218..3ea4344f0315 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h<br>
@@ -31,5 +31,7 @@ void mmhub_v2_0_init(struct amdgpu_device *adev);<br>
 int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,<br>
                                enum amd_clockgating_state state);<br>
 void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);<br>
+void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
+                               uint64_t page_table_base);<br>
 <br>
 #endif<br>
-- <br>
2.17.1<br>
<br>
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