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Thanks Feifei!<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Xu, Feifei <Feifei.Xu@amd.com><br>
<b>Sent:</b> Thursday, October 24, 2019 18:12<br>
<b>To:</b> Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Xiao, Jack <Jack.Xiao@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com><br>
<b>Subject:</b> RE: [PATCH 2/3] drm/amdgpu/gfx10: update gfx golden settings for navi14</font>
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<div class="PlainText">Series is reviewed-by: Feifei Xu <Feifei.Xu@amd.com><br>
<br>
Thanks,<br>
Feifei<br>
<br>
-----Original Message-----<br>
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tianci Yin<br>
Sent: Thursday, October 24, 2019 6:10 PM<br>
To: amd-gfx@lists.freedesktop.org<br>
Cc: Xu, Feifei <Feifei.Xu@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com><br>
Subject: [PATCH 2/3] drm/amdgpu/gfx10: update gfx golden settings for navi14<br>
<br>
From: "Tianci.Yin" <tianci.yin@amd.com><br>
<br>
update registers: mmCGTT_SPI_CLK_CTRL<br>
<br>
Change-Id: Ib2539aae1fb0d001278b7f89c90ad6296f9fb85f<br>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-<br>
1 file changed, 1 insertion(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index 11e863c4c40b..22d0fade9c71 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -140,7 +140,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),<br>
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),<br>
-- <br>
2.17.1<br>
<br>
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