<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body bgcolor="white" lang="EN-US" link="#0563C1" vlink="#954F72"> <div class="WordSection1"> [AMD Official Use Only - Internal Distribution Only]<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com> Sent: Wednesday, December 4, 2019 2:44 AM To: Ma, Le <Le.Ma@amd.com>; amd-gfx@lists.freedesktop.org; Zhou1, Tao <Tao.Zhou1@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Li, Dennis <Dennis.Li@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com> Cc: Chen, Guchun <Guchun.Chen@amd.com> Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI<o:p></o:p> </div> </div> <o:p> </o:p> Thanks Ma, this was very helpful as I am sill not able to setup XGMI hive with latest FW and VBIOS.<o:p></o:p> I traced the workqueue subsystem (full log attached). Specifically here is the life cycle of our 2 work items executing amdgpu_device_xgmi_reset_func bellow<o:p></o:p> [Le]: Thanks Andrey for the deep debug. Your feedback gave me a more profound understanding on this case. My comments split as below.<o:p></o:p> You were right to note they both run on came CPU (32) but they are executed by different threads. Also as you see by workqueue_execute_start/end timestamps they actually ran in parallel and not one after another even while being assigned to the same CPU and that because of thread preemption (there is at least psp_v11_0_mode1_reset->msleep(500)) which yields the CPU and hence allows the second work to run + I am sure that on preemptive kernel one reset work would be preempted at some point anyway and let the other run. <o:p></o:p> [Le]: Yes, from the trace log, the xgmi_reset_func items are assigned to different work threads bound to one same CPU. And you are right that cpu preemption will happen when msleep called which yield the CPU to allow second work to run. That’s a great founding😊. But it’s not a real parallel run to me because second work can only preempt to run when first work go to sleep. I made an experiment here to change this unique msleep to udelay, then second work item will run after first item finished in a serial execuation.<o:p></o:p> Now you had issues with BACO reset while the test I ran on your system is mode1 reset and so I assumed that maybe BACO has some non preempt-able busy wait which doesn't give a chance to second work item's thread to run on that CPU before the first finished - but from looking in the code I see smu_v11_0_baco_enter->msleep(10) so even in that case the first reset work item was supposed to yield CPU after BACO ENTER sent to SMU and let the other reset work do the same to the second card and so i don't see how even in this case there is a serial execution ?<o:p></o:p> [Le]: VG20 uses old powerplay framework (smu_v11_0_baco_enter->msleep(10) in swSMU framework), so no msleep and no CPU preemption. BACO reset has Enter/Exit 2 phases. We expect all the XGMI nodes enter BACO simultaneously instead of one after one as a serial execution, then exit BACO simultaneously.<o:p></o:p> P.S How you solution solves the case where the XGMI hive is bigger then number of CPUs on the system ? Assuming that what you say is correct and there is a serial execution when on the same CPU, if they hive is bigger then number of CPUs you will eventually get back to sending reset work to a CPU already executing BACO ENTER (or EXIT) for another device and will get the serialization problem anyway. <o:p></o:p> [Le]: Yeah, I also considered the situation that XGMI hive bigger than CPU NR. I think it’s an extreme situation and should not exist. However, assuming it exists, many work items scatter in several CPUs will be executed faster than bound to one same CPU, isn’t it ?<o:p></o:p> cat-3002 [032] d... 33153.791829: workqueue_queue_work: work struct=00000000e43c1ebb function=amdgpu_device_xgmi_reset_func [amdgpu] workqueue=0000000080331d91 req_cpu=8192 cpu=32 cat-3002 [032] d... 33153.791829: workqueue_activate_work: work struct 00000000e43c1ebb cat-3002 [032] dN.. 33153.791831: workqueue_queue_work: work struct=00000000e67113aa function=amdgpu_device_xgmi_reset_func [amdgpu] workqueue=0000000080331d91 req_cpu=8192 cpu=32 cat-3002 [032] dN.. 33153.791832: workqueue_activate_work: work struct 00000000e67113aa kworker/32:1H-551 [032] .... 33153.791834: workqueue_execute_start: work struct 00000000e43c1ebb: function amdgpu_device_xgmi_reset_func [amdgpu] kworker/32:0H-175 [032] .... 33153.792087: workqueue_execute_start: work struct 00000000e67113aa: function amdgpu_device_xgmi_reset_func [amdgpu] kworker/32:1H-551 [032] .... 33154.310948: workqueue_execute_end: work struct 00000000e43c1ebb kworker/32:0H-175 [032] .... 33154.311043: workqueue_execute_end: work struct 00000000e67113aa<o:p></o:p> Andrey<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <div> On 12/3/19 5:06 AM, Ma, Le wrote:<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> [AMD Official Use Only - Internal Distribution Only]<o:p></o:p> <o:p></o:p> Hi Andrey,<o:p></o:p> <o:p></o:p> You can try the XGMI system below:<o:p></o:p> IP: 10.67.69.53<o:p></o:p> U/P: jenkins/0<o:p></o:p> <o:p></o:p> The original drm-next kernel is installed.<o:p></o:p> <o:p></o:p> Regards,<o:p></o:p> Ma Le<o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Grodzovsky, Andrey <a href="mailto:Andrey.Grodzovsky@amd.com"><Andrey.Grodzovsky@amd.com></a> Sent: Tuesday, December 3, 2019 6:05 AM To: Ma, Le <a href="mailto:Le.Ma@amd.com"><Le.Ma@amd.com></a>; <a href="mailto:amd-gfx@lists.freedesktop.org"> amd-gfx@lists.freedesktop.org</a> Cc: Chen, Guchun <a href="mailto:Guchun.Chen@amd.com"><Guchun.Chen@amd.com></a>; Zhou1, Tao <a href="mailto:Tao.Zhou1@amd.com"><Tao.Zhou1@amd.com></a>; Deucher, Alexander <a href="mailto:Alexander.Deucher@amd.com"> <Alexander.Deucher@amd.com></a>; Li, Dennis <a href="mailto:Dennis.Li@amd.com"><Dennis.Li@amd.com></a>; Zhang, Hawking <a href="mailto:Hawking.Zhang@amd.com"><Hawking.Zhang@amd.com></a> Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI<o:p></o:p> </div> </div> <o:p></o:p> <o:p></o:p> <div> On 12/2/19 6:42 AM, Ma, Le wrote:<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> [AMD Official Use Only - Internal Distribution Only]<o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Grodzovsky, Andrey <a href="mailto:Andrey.Grodzovsky@amd.com"><Andrey.Grodzovsky@amd.com></a> Sent: Saturday, November 30, 2019 12:22 AM To: Ma, Le <a href="mailto:Le.Ma@amd.com"><Le.Ma@amd.com></a>; <a href="mailto:amd-gfx@lists.freedesktop.org"> amd-gfx@lists.freedesktop.org</a> Cc: Chen, Guchun <a href="mailto:Guchun.Chen@amd.com"><Guchun.Chen@amd.com></a>; Zhou1, Tao <a href="mailto:Tao.Zhou1@amd.com"><Tao.Zhou1@amd.com></a>; Deucher, Alexander <a href="mailto:Alexander.Deucher@amd.com"> <Alexander.Deucher@amd.com></a>; Li, Dennis <a href="mailto:Dennis.Li@amd.com"><Dennis.Li@amd.com></a>; Zhang, Hawking <a href="mailto:Hawking.Zhang@amd.com"><Hawking.Zhang@amd.com></a> Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI<o:p></o:p> </div> </div> <o:p></o:p> <o:p></o:p> <div> On 11/28/19 4:00 AM, Ma, Le wrote:<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <o:p></o:p> <o:p></o:p> -----Original Message----- From: Grodzovsky, Andrey <a href="mailto:Andrey.Grodzovsky@amd.com"><Andrey.Grodzovsky@amd.com></a> Sent: Wednesday, November 27, 2019 11:46 PM To: Ma, Le <a href="mailto:Le.Ma@amd.com"><Le.Ma@amd.com></a>; <a href="mailto:amd-gfx@lists.freedesktop.org"> amd-gfx@lists.freedesktop.org</a> Cc: Chen, Guchun <a href="mailto:Guchun.Chen@amd.com"><Guchun.Chen@amd.com></a>; Zhou1, Tao <a href="mailto:Tao.Zhou1@amd.com"><Tao.Zhou1@amd.com></a>; Deucher, Alexander <a href="mailto:Alexander.Deucher@amd.com"> <Alexander.Deucher@amd.com></a>; Li, Dennis <a href="mailto:Dennis.Li@amd.com"><Dennis.Li@amd.com></a>; Zhang, Hawking <a href="mailto:Hawking.Zhang@amd.com"><Hawking.Zhang@amd.com></a> Subject: Re: [PATCH 07/10] drm/amdgpu: add concurrent baco reset support for XGMI<o:p></o:p> <o:p></o:p> <o:p></o:p> On 11/27/19 4:15 AM, Le Ma wrote:<o:p></o:p> > Currently each XGMI node reset wq does not run in parrallel because <o:p></o:p> > same work item bound to same cpu runs in sequence. So change to bound <o:p></o:p> > the xgmi_reset_work item to different cpus.<o:p></o:p> <o:p></o:p> It's not the same work item, see more bellow<o:p></o:p> <o:p></o:p> <o:p></o:p> > <o:p></o:p> > XGMI requires all nodes enter into baco within very close proximity <o:p></o:p> > before any node exit baco. So schedule the xgmi_reset_work wq twice <o:p></o:p> > for enter/exit baco respectively.<o:p></o:p> > <o:p></o:p> > The default reset code path and methods do not change for vega20 production:<o:p></o:p> > - baco reset without xgmi/ras<o:p></o:p> > - psp reset with xgmi/ras<o:p></o:p> > <o:p></o:p> > To enable baco for XGMI/RAS case, both 2 conditions below are needed:<o:p></o:p> > - amdgpu_ras_enable=2<o:p></o:p> > - baco-supported smu firmware<o:p></o:p> > <o:p></o:p> > The case that PSP reset and baco reset coexist within an XGMI hive is <o:p></o:p> > not in the consideration.<o:p></o:p> > <o:p></o:p> > Change-Id: I9c08cf90134f940b42e20d2129ff87fba761c532<o:p></o:p> > Signed-off-by: Le Ma <<a href="mailto:le.ma@amd.com">le.ma@amd.com</a>><o:p></o:p> > ---<o:p></o:p> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +<o:p></o:p> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 78 ++++++++++++++++++++++++++----<o:p></o:p> > 2 files changed, 70 insertions(+), 10 deletions(-)<o:p></o:p> > <o:p></o:p> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h <o:p></o:p> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<o:p></o:p> > index d120fe5..08929e6 100644<o:p></o:p> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h<o:p></o:p> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<o:p></o:p> > @@ -998,6 +998,8 @@ struct amdgpu_device {<o:p></o:p> > int pstate;<o:p></o:p> > /* enable runtime pm on the device */<o:p></o:p> > bool runpm;<o:p></o:p> > +<o:p></o:p> > + bool in_baco;<o:p></o:p> > };<o:p></o:p> > <o:p></o:p> > static inline struct amdgpu_device *amdgpu_ttm_adev(struct <o:p></o:p> > ttm_bo_device *bdev) diff --git <o:p></o:p> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c <o:p></o:p> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<o:p></o:p> > index bd387bb..71abfe9 100644<o:p></o:p> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<o:p></o:p> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<o:p></o:p> > @@ -2654,7 +2654,13 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)<o:p></o:p> > struct amdgpu_device *adev =<o:p></o:p> > container_of(__work, struct amdgpu_device, xgmi_reset_work);<o:p></o:p> > <o:p></o:p> > - adev->asic_reset_res = amdgpu_asic_reset(adev);<o:p></o:p> > + if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)<o:p></o:p> > + adev->asic_reset_res = (adev->in_baco == false) ?<o:p></o:p> > + amdgpu_device_baco_enter(adev->ddev) :<o:p></o:p> > + amdgpu_device_baco_exit(adev->ddev);<o:p></o:p> > + else<o:p></o:p> > + adev->asic_reset_res = amdgpu_asic_reset(adev);<o:p></o:p> > +<o:p></o:p> > if (adev->asic_reset_res)<o:p></o:p> > DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",<o:p></o:p> > adev->asic_reset_res, adev->ddev->unique); @@ -3796,6 +3802,7 @@ <o:p></o:p> > static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,<o:p></o:p> > struct amdgpu_device *tmp_adev = NULL;<o:p></o:p> > bool need_full_reset = *need_full_reset_arg, vram_lost = false;<o:p></o:p> > int r = 0;<o:p></o:p> > + int cpu = smp_processor_id();<o:p></o:p> > <o:p></o:p> > /*<o:p></o:p> > * ASIC reset has to be done on all HGMI hive nodes ASAP @@ <o:p></o:p> > -3803,21 +3810,24 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,<o:p></o:p> > */<o:p></o:p> > if (need_full_reset) {<o:p></o:p> > list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {<o:p></o:p> > - /* For XGMI run all resets in parallel to speed up the process */<o:p></o:p> > + /*<o:p></o:p> > + * For XGMI run all resets in parallel to speed up the<o:p></o:p> > + * process by scheduling the highpri wq on different<o:p></o:p> > + * cpus. For XGMI with baco reset, all nodes must enter<o:p></o:p> > + * baco within close proximity before anyone exit.<o:p></o:p> > + */<o:p></o:p> > if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {<o:p></o:p> > - if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))<o:p></o:p> <o:p></o:p> <o:p></o:p> Note that tmp_adev->xgmi_reset_work (the work item) is per device in XGMI hive and not the same work item. So I don't see why you need to explicitly queue them on different CPUs, they should run in parallel already.<o:p></o:p> <o:p></o:p> Andrey<o:p></o:p> <o:p></o:p> [Le]: It’s also beyond my understanding that the 2 node reset work items scheduled to same cpu does not run in parallel. But from the experiment result in my side, the 2nd work item always run after 1st work item finished. Based on this result, I changed to queue them on different CPUs to make sure more XGMI nodes case to run in parallel, because baco requires all nodes enter baco within very close proximity. <o:p></o:p> <o:p></o:p> The experiment code is as following for your reference. When card0 worker running, card1 worker is not observed to run.<o:p></o:p> </blockquote> <o:p></o:p> The code bellow will only test that they don't run concurrently - but this doesn't mean they don't run on different CPUs and threads,I don't have an XGMI setup at hand to test this theory but what if there is some locking dependency between them that serializes their execution ? Can you just add a one line print inside amdgpu_device_xgmi_reset_func that prints CPU id, thread name/id and card number ?<o:p></o:p> Andrey<o:p></o:p> [Le]: I checked if directly use queue_work() several times, the same CPU thread will be used. And the worker per CPU will execute the item one by one. Our goal here is to make the xgmi_reset_func run concurrently for XGMI BACO case. That’s why I schedule them on different CPUs to run parallelly. And I can share the XGMI system with you if you’d like to verify more.<o:p></o:p> </blockquote> <o:p></o:p> I tried today to setup XGMI 2P setup to test this but weren't able to load with the XGMI bridge in place (maybe faulty bridge) - so yea - maybe leave me your setup before your changes (the original code) so i can try to open some kernel traces that show CPU id and thread id to check this. It's just so weird that system_highpri_wq which is documented to be multi-cpu and multi-threaded wouldn't queue those work items to different cpus and worker threads.<o:p></o:p> Andrey<o:p></o:p> <o:p></o:p> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <o:p></o:p> +atomic_t card0_in_baco = ATOMIC_INIT(0);<o:p></o:p> +atomic_t card1_in_baco = ATOMIC_INIT(0);<o:p></o:p> +<o:p></o:p> static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)<o:p></o:p> {<o:p></o:p> struct amdgpu_device *adev =<o:p></o:p> container_of(__work, struct amdgpu_device, xgmi_reset_work);<o:p></o:p> <o:p></o:p> + printk("lema1: card 0x%x goes into reset wq\n", adev->pdev->bus->number);<o:p></o:p> + if (adev->pdev->bus->number == 0x7) {<o:p></o:p> + atomic_set(&card1_in_baco, 1);<o:p></o:p> + printk("lema1: card1 in baco from card1 view\n");<o:p></o:p> + }<o:p></o:p> +<o:p></o:p> if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)<o:p></o:p> adev->asic_reset_res = (adev->in_baco == false) ?<o:p></o:p> amdgpu_device_baco_enter(adev->ddev) :<o:p></o:p> @@ -2664,6 +2673,23 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)<o:p></o:p> if (adev->asic_reset_res)<o:p></o:p> DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",<o:p></o:p> adev->asic_reset_res, adev->ddev->unique);<o:p></o:p> +<o:p></o:p> + if (adev->pdev->bus->number == 0x4) {<o:p></o:p> + atomic_set(&card0_in_baco, 1);<o:p></o:p> + printk("lema1: card0 in baco from card0 view\n");<o:p></o:p> +<o:p></o:p> + while (true)<o:p></o:p> + if (!!atomic_read(&card1_in_baco))<o:p></o:p> + break;<o:p></o:p> + printk("lema1: card1 in baco from card0 view\n");<o:p></o:p> + }<o:p></o:p> +<o:p></o:p> + if (adev->pdev->bus->number == 0x7) {<o:p></o:p> + while (true)<o:p></o:p> + if (!!atomic_read(&card0_in_baco))<o:p></o:p> + break;<o:p></o:p> + printk("lema1: card0 in baco from card1 view\n");<o:p></o:p> + }<o:p></o:p> <o:p></o:p> > + if (!queue_work_on(cpu, system_highpri_wq,<o:p></o:p> > + &tmp_adev->xgmi_reset_work))<o:p></o:p> > r = -EALREADY;<o:p></o:p> > + cpu = cpumask_next(cpu, cpu_online_mask);<o:p></o:p> > } else<o:p></o:p> > r = amdgpu_asic_reset(tmp_adev);<o:p></o:p> > -<o:p></o:p> > - if (r) {<o:p></o:p> > - DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",<o:p></o:p> > - r, tmp_adev->ddev->unique);<o:p></o:p> > + if (r)<o:p></o:p> > break;<o:p></o:p> > - }<o:p></o:p> > }<o:p></o:p> > <o:p></o:p> > - /* For XGMI wait for all PSP resets to complete before proceed */<o:p></o:p> > + /* For XGMI wait for all work to complete before proceed */<o:p></o:p> > if (!r) {<o:p></o:p> > list_for_each_entry(tmp_adev, device_list_handle,<o:p></o:p> > gmc.xgmi.head) {<o:p></o:p> > @@ -3826,11 +3836,59 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,<o:p></o:p> > r = tmp_adev->asic_reset_res;<o:p></o:p> > if (r)<o:p></o:p> > break;<o:p></o:p> > + if(AMD_RESET_METHOD_BACO ==<o:p></o:p> > + amdgpu_asic_reset_method(tmp_adev))<o:p></o:p> > + tmp_adev->in_baco = true;<o:p></o:p> > }<o:p></o:p> > }<o:p></o:p> > }<o:p></o:p> > - }<o:p></o:p> > <o:p></o:p> > + /*<o:p></o:p> > + * For XGMI with baco reset, need exit baco phase by scheduling<o:p></o:p> > + * xgmi_reset_work one more time. PSP reset skips this phase.<o:p></o:p> > + * Not assume the situation that PSP reset and baco reset<o:p></o:p> > + * coexist within an XGMI hive.<o:p></o:p> > + */<o:p></o:p> > +<o:p></o:p> > + if (!r) {<o:p></o:p> > + cpu = smp_processor_id();<o:p></o:p> > + list_for_each_entry(tmp_adev, device_list_handle,<o:p></o:p> > + gmc.xgmi.head) {<o:p></o:p> > + if (tmp_adev->gmc.xgmi.num_physical_nodes > 1<o:p></o:p> > + && AMD_RESET_METHOD_BACO ==<o:p></o:p> > + amdgpu_asic_reset_method(tmp_adev)) {<o:p></o:p> > + if (!queue_work_on(cpu,<o:p></o:p> > + system_highpri_wq,<o:p></o:p> > + &tmp_adev->xgmi_reset_work))<o:p></o:p> > + r = -EALREADY;<o:p></o:p> > + if (r)<o:p></o:p> > + break;<o:p></o:p> > + cpu = cpumask_next(cpu, cpu_online_mask);<o:p></o:p> > + }<o:p></o:p> > + }<o:p></o:p> > + }<o:p></o:p> > +<o:p></o:p> > + if (!r) {<o:p></o:p> > + list_for_each_entry(tmp_adev, device_list_handle,<o:p></o:p> > + gmc.xgmi.head) {<o:p></o:p> > + if (tmp_adev->gmc.xgmi.num_physical_nodes > 1<o:p></o:p> > + && AMD_RESET_METHOD_BACO ==<o:p></o:p> > + amdgpu_asic_reset_method(tmp_adev)) {<o:p></o:p> > + flush_work(&tmp_adev->xgmi_reset_work);<o:p></o:p> > + r = tmp_adev->asic_reset_res;<o:p></o:p> > + if (r)<o:p></o:p> > + break;<o:p></o:p> > + tmp_adev->in_baco = false;<o:p></o:p> > + }<o:p></o:p> > + }<o:p></o:p> > + }<o:p></o:p> > +<o:p></o:p> > + if (r) {<o:p></o:p> > + DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",<o:p></o:p> > + r, tmp_adev->ddev->unique);<o:p></o:p> > + goto end;<o:p></o:p> > + }<o:p></o:p> > + }<o:p></o:p> > <o:p></o:p> > list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {<o:p></o:p> > if (need_full_reset) {<o:p></o:p> </blockquote> </blockquote> </blockquote> </div> </body> </html>