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[AMD Official Use Only - Internal Distribution Only]<br>
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Thanks Feifei!<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Xu, Feifei <Feifei.Xu@amd.com><br>
<b>Sent:</b> Wednesday, December 11, 2019 11:29<br>
<b>To:</b> Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; Long, Gang <Gang.Long@amd.com>; Li, Pauline <Pauline.Li@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com><br>
<b>Subject:</b> RE: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings</font>
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Series is Reviewed-by: Feifei Xu <Feifei Xu@amd.com><br>
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-----Original Message-----<br>
From: Tianci Yin <tianci.yin@amd.com> <br>
Sent: Wednesday, December 11, 2019 11:22 AM<br>
To: amd-gfx@lists.freedesktop.org<br>
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; Long, Gang <Gang.Long@amd.com>; Li, Pauline <Pauline.Li@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com><br>
Subject: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings<br>
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From: "Tianci.Yin" <tianci.yin@amd.com><br>
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add registers: mmSPI_CONFIG_CNTL<br>
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Signed-off-by: Tianci.Yin <tianci.yin@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +<br>
1 file changed, 1 insertion(+)<br>
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diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index ed630d37c32c..f3324fa4e194 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -114,6 +114,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),<br>
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),<br>
-- <br>
2.17.1<br>
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