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<p class="msipheadera92e061b" style="margin:0in;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">-----Original Message-----<br>
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com> <br>
Sent: Thursday, December 12, 2019 4:39 AM<br>
To: dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org<br>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Ma, Le <Le.Ma@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com><br>
Subject: [RESEND PATCH 4/5] Subject: drm/amdgpu: Redo XGMI reset synchronization.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Use task barrier in XGMI hive to synchronize ASIC resets across devices in XGMI hive.<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">Signed-off-by: Andrey Grodzovsky <<a href="mailto:andrey.grodzovsky@amd.com"><span style="color:windowtext;text-decoration:none">andrey.grodzovsky@amd.com</span></a>><o:p></o:p></p>
<p class="MsoPlainText">---<o:p></o:p></p>
<p class="MsoPlainText">drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 +++++++++++++++++++++++++-----<o:p></o:p></p>
<p class="MsoPlainText">1 file changed, 36 insertions(+), 6 deletions(-)<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<o:p></o:p></p>
<p class="MsoPlainText">index 1d19edfa..e4089a0 100644<o:p></o:p></p>
<p class="MsoPlainText">--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<o:p></o:p></p>
<p class="MsoPlainText">+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<o:p></o:p></p>
<p class="MsoPlainText">@@ -67,6 +67,7 @@<o:p></o:p></p>
<p class="MsoPlainText">#include "amdgpu_tmz.h"<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"> #include <linux/suspend.h><o:p></o:p></p>
<p class="MsoPlainText">+#include <drm/task_barrier.h><o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText"> MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");<o:p></o:p></p>
<p class="MsoPlainText">MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");<o:p></o:p></p>
<p class="MsoPlainText">@@ -2663,14 +2664,43 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) {<o:p></o:p></p>
<p class="MsoPlainText"> struct amdgpu_device *adev =<o:p></o:p></p>
<p class="MsoPlainText"> container_of(__work, struct amdgpu_device, xgmi_reset_work);<o:p></o:p></p>
<p class="MsoPlainText">+ struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">- if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)<o:p></o:p></p>
<p class="MsoPlainText">- adev->asic_reset_res = (adev->in_baco == false) ?<o:p></o:p></p>
<p class="MsoPlainText">- amdgpu_device_baco_enter(adev->ddev) :<o:p></o:p></p>
<p class="MsoPlainText">- qamdgpu_device_baco_exit(adev->ddev);<o:p></o:p></p>
<p class="MsoPlainText">- else<o:p></o:p></p>
<p class="MsoPlainText">- adev->asic_reset_res = amdgpu_asic_reset(adev);<o:p></o:p></p>
<p class="MsoPlainText">+ /*<o:p></o:p></p>
<p class="MsoPlainText">+ * Use task barrier to synchronize all xgmi reset works across the<o:p></o:p></p>
<p class="MsoPlainText">+ * hive.<o:p></o:p></p>
<p class="MsoPlainText">+ * task_barrier_enter and task_barrier_exit will block untill all the<o:p></o:p></p>
<p class="MsoPlainText">+ * threads running the xgmi reset works reach those points. I assume<o:p></o:p></p>
<p class="MsoPlainText">+ * guarantee of progress here for all the threads as the workqueue code<o:p></o:p></p>
<p class="MsoPlainText">+ * creates new worker threads as needed by amount of work items in queue<o:p></o:p></p>
<p class="MsoPlainText">+ * (see worker_thread) and also each thread sleeps in the barrir and by<o:p></o:p></p>
<p class="MsoPlainText">+ * this yielding the CPU for other work threads to make progress.<o:p></o:p></p>
<p class="MsoPlainText">+ */<o:p></o:p></p>
<p class="MsoPlainText"><span style="color:#203864">[Le]: This comments can be adjusted since we switch to system_unbound_wq in patch #5.<o:p></o:p></span></p>
<p class="MsoPlainText">+ if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {<o:p></o:p></p>
<p class="MsoPlainText">+<o:p></o:p></p>
<p class="MsoPlainText">+ if (hive)<o:p></o:p></p>
<p class="MsoPlainText">+ task_barrier_enter(&hive->tb);<o:p></o:p></p>
<p class="MsoPlainText"><span style="color:#203864">[Le]: The multiple hive condition can be checked only once and moved to the location right after the assignment.<o:p></o:p></span></p>
<p class="MsoPlainText">+<o:p></o:p></p>
<p class="MsoPlainText">+ adev->asic_reset_res = amdgpu_device_baco_enter(adev->ddev);<o:p></o:p></p>
<p class="MsoPlainText">+<o:p></o:p></p>
<p class="MsoPlainText">+ if (adev->asic_reset_res)<o:p></o:p></p>
<p class="MsoPlainText">+ goto fail;<o:p></o:p></p>
<p class="MsoPlainText">+<o:p></o:p></p>
<p class="MsoPlainText">+ if (hive)<o:p></o:p></p>
<p class="MsoPlainText">+ task_barrier_exit(&hive->tb);<o:p></o:p></p>
<p class="MsoPlainText"><span style="color:#203864">[Le]: Same as above.<o:p></o:p></span></p>
<p class="MsoPlainText">+<o:p></o:p></p>
<p class="MsoPlainText">+ adev->asic_reset_res = amdgpu_device_baco_exit(adev->ddev);<o:p></o:p></p>
<p class="MsoPlainText">+<o:p></o:p></p>
<p class="MsoPlainText">+ if (adev->asic_reset_res)<o:p></o:p></p>
<p class="MsoPlainText">+ goto fail;<o:p></o:p></p>
<p class="MsoPlainText">+ } else {<o:p></o:p></p>
<p class="MsoPlainText">+ if (hive)<o:p></o:p></p>
<p class="MsoPlainText">+ task_barrier_full(&hive->tb);<o:p></o:p></p>
<p class="MsoPlainText"><span style="color:#203864">[Le]: Same as above.<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="color:#203864"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span style="color:#203864">With above addressed, Reviewed-by: Le Ma <<a href="mailto:Le.Ma@amd.com"><span style="color:#033160">Le.Ma@amd.com</span></a>><o:p></o:p></span></p>
<p class="MsoPlainText"><span style="color:#203864"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span style="color:#203864">Regards,<o:p></o:p></span></p>
<p class="MsoPlainText"><span style="color:#203864">Ma Le<o:p></o:p></span></p>
<p class="MsoPlainText">+<o:p></o:p></p>
<p class="MsoPlainText">+ adev->asic_reset_res = amdgpu_asic_reset(adev);<o:p></o:p></p>
<p class="MsoPlainText">+ }<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
<p class="MsoPlainText">+fail:<o:p></o:p></p>
<p class="MsoPlainText"> if (adev->asic_reset_res)<o:p></o:p></p>
<p class="MsoPlainText"> DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",<o:p></o:p></p>
<p class="MsoPlainText"> adev->asic_reset_res, adev->ddev->unique);<o:p></o:p></p>
<p class="MsoPlainText">--<o:p></o:p></p>
<p class="MsoPlainText">2.7.4<o:p></o:p></p>
<p class="MsoPlainText"><o:p> </o:p></p>
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